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Performance analysis of RISC-V based cores in a dual-core programmable logic controller.

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Bibliographic Details
Title: Performance analysis of RISC-V based cores in a dual-core programmable logic controller.
Authors: JEKOT, Bartlomiej1, KORZUCH, Blazej1, OLES, Fabian1, LEMPA, Pawel1, STAJER, Oskar1, PRZECHOWSKI, Rafal1, CZERWINSKI, Robert1, CHMIEL, Miroslaw1 mchmiel@polsl.pl
Source: Bulletin of the Polish Academy of Sciences: Technical Sciences. 2026, Vol. 74 Issue 4, p1-11. 11p.
Database: Academic Search Ultimate
Description
ISSN:02397528
DOI:10.24425/bpasts.2026.158308