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Performance analysis of RISC-V based cores in a dual-core programmable logic controller.

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Title: Performance analysis of RISC-V based cores in a dual-core programmable logic controller.
Authors: JEKOT, Bartlomiej1, KORZUCH, Blazej1, OLES, Fabian1, LEMPA, Pawel1, STAJER, Oskar1, PRZECHOWSKI, Rafal1, CZERWINSKI, Robert1, CHMIEL, Miroslaw1 mchmiel@polsl.pl
Source: Bulletin of the Polish Academy of Sciences: Technical Sciences. 2026, Vol. 74 Issue 4, p1-11. 11p.
Database: Academic Search Ultimate
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DbLabel: Academic Search Ultimate
An: 195529177
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PubType: Academic Journal
PubTypeId: academicJournal
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  Data: Performance analysis of RISC-V based cores in a dual-core programmable logic controller.
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  Data: <searchLink fieldCode="JN" term="%22Bulletin+of+the+Polish+Academy+of+Sciences%3A+Technical+Sciences%22">Bulletin of the Polish Academy of Sciences: Technical Sciences</searchLink>. 2026, Vol. 74 Issue 4, p1-11. 11p.
PLink https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=asn&AN=195529177
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      – Type: doi
        Value: 10.24425/bpasts.2026.158308
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      – Code: eng
        Text: English
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        PageCount: 11
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      – TitleFull: Performance analysis of RISC-V based cores in a dual-core programmable logic controller.
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              M: 07
              Text: 2026
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              Y: 2026
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            – TitleFull: Bulletin of the Polish Academy of Sciences: Technical Sciences
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