Quaternary NAND Gate Simulation Using SWS-FETS and Pseudo Logic Gates.
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| Title: | Quaternary NAND Gate Simulation Using SWS-FETS and Pseudo Logic Gates. |
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| Authors: | Saman, Bander1 (AUTHOR) saman@tu.edu.sa, Chandy, J.2 (AUTHOR) john.chandy@uconn.edu, Jain, F. C.2 (AUTHOR) fcj@engr.uconn.edu |
| Source: | International Journal of High Speed Electronics & Systems. Mar2026, Vol. 35 Issue 1, p1-12. 12p. |
| Database: | Business Source Ultimate |
| ISSN: | 01291564 |
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| DOI: | 10.1142/S0129156426400070 |
