APA (7th ed.) Citation

Jayaraj, B., & Gopalan, K. (2025). Efficient Multiply-Accumulate Unit Using High-Speed and Low Power Vedic Multiplier for Digital Signal Processors Applications. Traitement du Signal, 42(6), 3637. https://doi.org/10.18280/ts.420645

Chicago Style (17th ed.) Citation

Jayaraj, Banumathi, and Karthy Gopalan. "Efficient Multiply-Accumulate Unit Using High-Speed and Low Power Vedic Multiplier for Digital Signal Processors Applications." Traitement Du Signal 42, no. 6 (2025): 3637. https://doi.org/10.18280/ts.420645.

MLA (9th ed.) Citation

Jayaraj, Banumathi, and Karthy Gopalan. "Efficient Multiply-Accumulate Unit Using High-Speed and Low Power Vedic Multiplier for Digital Signal Processors Applications." Traitement Du Signal, vol. 42, no. 6, 2025, p. 3637, https://doi.org/10.18280/ts.420645.