Simulation of semiconductor wafer dicing induced faults on chips and their application as augmentation method for a deep learning based visual inspection system.

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Bibliographic Details
Title: Simulation of semiconductor wafer dicing induced faults on chips and their application as augmentation method for a deep learning based visual inspection system.
Authors: Friedrich, Michael1 (AUTHOR) michael.friedrich@cs.tu-chemnitz.de, Schlosser, Tobias1 (AUTHOR) tobias.schlosser@cs.tu-chemnitz.de, Kowerko, Danny1 (AUTHOR) danny.kowerko@cs.tu-chemnitz.de
Source: Journal of Intelligent Manufacturing. Feb2026, Vol. 37 Issue 2, p573-596. 24p.
Database: Business Source Ultimate
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ISSN:09565515
DOI:10.1007/s10845-024-02559-0