FPGA based design and performance evaluation of 32-bit hybrid carry select adder architectures.
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| Title: | FPGA based design and performance evaluation of 32-bit hybrid carry select adder architectures. |
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| Authors: | Thamizharasan, V.1 (AUTHOR) ecetamil@gmail.com, Parthipan, V.2 (AUTHOR) |
| Source: | International Journal of Electronics. Apr2026, Vol. 113 Issue 4, p666-694. 29p. |
| Database: | Business Source Ultimate |
| ISSN: | 00207217 |
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| DOI: | 10.1080/00207217.2025.2549949 |
