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FPGA based design and performance evaluation of 32-bit hybrid carry select adder architectures.

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Title: FPGA based design and performance evaluation of 32-bit hybrid carry select adder architectures.
Authors: Thamizharasan, V.1 (AUTHOR) ecetamil@gmail.com, Parthipan, V.2 (AUTHOR)
Source: International Journal of Electronics. Apr2026, Vol. 113 Issue 4, p666-694. 29p.
Database: Business Source Ultimate
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Header DbId: bsu
DbLabel: Business Source Ultimate
An: 192172513
AccessLevel: 2
PubType: Academic Journal
PubTypeId: academicJournal
PreciseRelevancyScore: 0
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  Data: FPGA based design and performance evaluation of 32-bit hybrid carry select adder architectures.
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  Data: <searchLink fieldCode="JN" term="%22International+Journal+of+Electronics%22">International Journal of Electronics</searchLink>. Apr2026, Vol. 113 Issue 4, p666-694. 29p.
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RecordInfo BibRecord:
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      – Type: doi
        Value: 10.1080/00207217.2025.2549949
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      – Code: eng
        Text: English
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        PageCount: 29
        StartPage: 666
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      – TitleFull: FPGA based design and performance evaluation of 32-bit hybrid carry select adder architectures.
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              Text: Apr2026
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              Y: 2026
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