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A Hardware Scheduler Based on Task Queues for FPGA-Based Embedded Real-Time Systems.

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Bibliographic Details
Title: A Hardware Scheduler Based on Task Queues for FPGA-Based Embedded Real-Time Systems.
Authors: Tang, Yi1, Bergmann, Neil W.2
Source: IEEE Transactions on Computers. May2015, Vol. 64 Issue 5, p1254-1267. 14p.
Subjects: Microprocessor performance, Field programmable gate arrays, Computer input-output equipment, Computer scheduling, Queuing theory, Algorithms
Abstract: A hardware scheduler is developed to improve real-time performance of soft-core processor based computing systems. A hardware scheduler typically accelerates system performance at the cost of increased hardware resources, inflexibility and integration difficulty. However, the reprogrammability of FPGA-based systems removes the problems of inflexibility and integration difficulty. This paper introduces a new task-queue architecture to better support practical task controls and maintain good resource scaling. The scheduler can be configured to support various algorithms such as time sliced priority scheduling, Earliest Deadline First and Least Slack Time. The hardware scheduler reduces scheduling overhead by more than 1,000 clock cycles and raises the system utilization bound by a maximum 19.2 percent. Scheduling jitter is reduced from hundreds of clock cycles in software to just two or three cycles for most operations. The additional resource cost is no more than 17 percent of a typical softcore system for a small scale embedded application. [ABSTRACT FROM PUBLISHER]
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Database: Engineering Source
Description
Abstract:A hardware scheduler is developed to improve real-time performance of soft-core processor based computing systems. A hardware scheduler typically accelerates system performance at the cost of increased hardware resources, inflexibility and integration difficulty. However, the reprogrammability of FPGA-based systems removes the problems of inflexibility and integration difficulty. This paper introduces a new task-queue architecture to better support practical task controls and maintain good resource scaling. The scheduler can be configured to support various algorithms such as time sliced priority scheduling, Earliest Deadline First and Least Slack Time. The hardware scheduler reduces scheduling overhead by more than 1,000 clock cycles and raises the system utilization bound by a maximum 19.2 percent. Scheduling jitter is reduced from hundreds of clock cycles in software to just two or three cycles for most operations. The additional resource cost is no more than 17 percent of a typical softcore system for a small scale embedded application. [ABSTRACT FROM PUBLISHER]
ISSN:00189340
DOI:10.1109/TC.2014.2315637