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A Hardware Scheduler Based on Task Queues for FPGA-Based Embedded Real-Time Systems.

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Title: A Hardware Scheduler Based on Task Queues for FPGA-Based Embedded Real-Time Systems.
Authors: Tang, Yi1, Bergmann, Neil W.2
Source: IEEE Transactions on Computers. May2015, Vol. 64 Issue 5, p1254-1267. 14p.
Subjects: Microprocessor performance, Field programmable gate arrays, Computer input-output equipment, Computer scheduling, Queuing theory, Algorithms
Abstract: A hardware scheduler is developed to improve real-time performance of soft-core processor based computing systems. A hardware scheduler typically accelerates system performance at the cost of increased hardware resources, inflexibility and integration difficulty. However, the reprogrammability of FPGA-based systems removes the problems of inflexibility and integration difficulty. This paper introduces a new task-queue architecture to better support practical task controls and maintain good resource scaling. The scheduler can be configured to support various algorithms such as time sliced priority scheduling, Earliest Deadline First and Least Slack Time. The hardware scheduler reduces scheduling overhead by more than 1,000 clock cycles and raises the system utilization bound by a maximum 19.2 percent. Scheduling jitter is reduced from hundreds of clock cycles in software to just two or three cycles for most operations. The additional resource cost is no more than 17 percent of a typical softcore system for a small scale embedded application. [ABSTRACT FROM PUBLISHER]
Copyright of IEEE Transactions on Computers is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
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  Data: A Hardware Scheduler Based on Task Queues for FPGA-Based Embedded Real-Time Systems.
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  Data: <searchLink fieldCode="DE" term="%22Microprocessor+performance%22">Microprocessor performance</searchLink><br /><searchLink fieldCode="DE" term="%22Field+programmable+gate+arrays%22">Field programmable gate arrays</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+input-output+equipment%22">Computer input-output equipment</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+scheduling%22">Computer scheduling</searchLink><br /><searchLink fieldCode="DE" term="%22Queuing+theory%22">Queuing theory</searchLink><br /><searchLink fieldCode="DE" term="%22Algorithms%22">Algorithms</searchLink>
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  Data: A hardware scheduler is developed to improve real-time performance of soft-core processor based computing systems. A hardware scheduler typically accelerates system performance at the cost of increased hardware resources, inflexibility and integration difficulty. However, the reprogrammability of FPGA-based systems removes the problems of inflexibility and integration difficulty. This paper introduces a new task-queue architecture to better support practical task controls and maintain good resource scaling. The scheduler can be configured to support various algorithms such as time sliced priority scheduling, Earliest Deadline First and Least Slack Time. The hardware scheduler reduces scheduling overhead by more than 1,000 clock cycles and raises the system utilization bound by a maximum 19.2 percent. Scheduling jitter is reduced from hundreds of clock cycles in software to just two or three cycles for most operations. The additional resource cost is no more than 17 percent of a typical softcore system for a small scale embedded application. [ABSTRACT FROM PUBLISHER]
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  Data: <i>Copyright of IEEE Transactions on Computers is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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        Value: 10.1109/TC.2014.2315637
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        Text: English
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        PageCount: 14
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      – SubjectFull: Microprocessor performance
        Type: general
      – SubjectFull: Field programmable gate arrays
        Type: general
      – SubjectFull: Computer input-output equipment
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      – SubjectFull: Computer scheduling
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      – SubjectFull: Queuing theory
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      – SubjectFull: Algorithms
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              Text: May2015
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