A methodology for speeding up matrix vector multiplication for single/multi-core architectures.

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Bibliographic Details
Title:	A methodology for speeding up matrix vector multiplication for single/multi-core architectures.
Authors:	Kelefouras, Vasilios¹ kelefouras@ece.upatras.gr, Kritikakou, Angeliki², Papadima, Elissavet¹, Goutis, Costas¹
Source:	Journal of Supercomputing. Jul2015, Vol. 71 Issue 7, p2644-2667. 24p.
Subjects:	Complex multiplication, SIMD (Computer architecture), Multicore processors, Cache memory, Computer memory management
Abstract:	In this paper, a new methodology for computing the Dense Matrix Vector Multiplication, for both embedded (processors without SIMD unit) and general purpose processors (single and multi-core processors, with SIMD unit), is presented. This methodology achieves higher execution speed than ATLAS state-of-the-art library (speedup from 1.2 up to 1.45). This is achieved by fully exploiting the combination of the software (e.g., data reuse) and hardware parameters (e.g., data cache associativity) which are considered simultaneously as one problem and not separately, giving a smaller search space and high-quality solutions. The proposed methodology produces a different schedule for different values of the (i) number of the levels of data cache; (ii) data cache sizes; (iii) data cache associativities; (iv) data cache and main memory latencies; (v) data array layout of the matrix and (vi) number of cores. [ABSTRACT FROM AUTHOR]
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Database:	Engineering Source

Description
Abstract:	In this paper, a new methodology for computing the Dense Matrix Vector Multiplication, for both embedded (processors without SIMD unit) and general purpose processors (single and multi-core processors, with SIMD unit), is presented. This methodology achieves higher execution speed than ATLAS state-of-the-art library (speedup from 1.2 up to 1.45). This is achieved by fully exploiting the combination of the software (e.g., data reuse) and hardware parameters (e.g., data cache associativity) which are considered simultaneously as one problem and not separately, giving a smaller search space and high-quality solutions. The proposed methodology produces a different schedule for different values of the (i) number of the levels of data cache; (ii) data cache sizes; (iii) data cache associativities; (iv) data cache and main memory latencies; (v) data array layout of the matrix and (vi) number of cores. [ABSTRACT FROM AUTHOR]
ISSN:	09208542
DOI:	10.1007/s11227-015-1409-9