PS directory: a scalable multilevel directory cache for CMPs.
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| Title: | PS directory: a scalable multilevel directory cache for CMPs. |
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| Authors: | Valls, Joan1 joavalmo@fiv.upv.es, Ros, Alberto2 aros@ditec.um.es, Sahuquillo, Julio1 jsahuqui@disca.upv.es, Gómez, María1 megomez@disca.upv.es |
| Source: | Journal of Supercomputing. Aug2015, Vol. 71 Issue 8, p2847-2876. 30p. |
| Subjects: | Performance of multiprocessors, Directory services (Computer network technology), Scalability, Computer networks, Energy consumption, Static random access memory chips |
| Abstract: | As the number of cores increases in current and future chip-multiprocessor (CMP) generations, coherence protocols must rely on novel hardware structures to scale in terms of performance, power, and area. Systems that use directory information for coherence purposes are currently the most scalable alternative. This paper studies the important differences between the directory behavior of private and shared blocks, which claim for a separate management of both types of blocks at the directory. We propose the PS directory, a two-level directory cache that keeps the reduced number of frequently accessed shared entries in a small and fast first-level cache, namely Shared cache, and uses a larger and slower second-level Private cache to track the large amount of private blocks. Entries in the Private cache do not implement the sharer vector, which allows important silicon area savings. Speed and area reasons suggest the use of eDRAM technology, much denser but slower than SRAM technology, for the Private cache, which in turn brings energy savings. Experimental results for a 16-core CMP show that, compared to a conventional directory, the PS directory improves performance by 14 $$\%$$ while reducing silicon area and energy consumption by 34 and 27 $$\%$$ , respectively. Also, compared to the state-of-the-art Multi-Grain Directory, the PS directory apart from increasing performance, it reduces power by 18.7 $$\%$$ , and provides more scalability in terms of area. [ABSTRACT FROM AUTHOR] |
| Copyright of Journal of Supercomputing is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
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| Header | DbId: egs DbLabel: Engineering Source An: 108563992 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: PS directory: a scalable multilevel directory cache for CMPs. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Valls%2C+Joan%22">Valls, Joan</searchLink><relatesTo>1</relatesTo><i> joavalmo@fiv.upv.es</i><br /><searchLink fieldCode="AR" term="%22Ros%2C+Alberto%22">Ros, Alberto</searchLink><relatesTo>2</relatesTo><i> aros@ditec.um.es</i><br /><searchLink fieldCode="AR" term="%22Sahuquillo%2C+Julio%22">Sahuquillo, Julio</searchLink><relatesTo>1</relatesTo><i> jsahuqui@disca.upv.es</i><br /><searchLink fieldCode="AR" term="%22Gómez%2C+María%22">Gómez, María</searchLink><relatesTo>1</relatesTo><i> megomez@disca.upv.es</i> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22Journal+of+Supercomputing%22">Journal of Supercomputing</searchLink>. Aug2015, Vol. 71 Issue 8, p2847-2876. 30p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Performance+of+multiprocessors%22">Performance of multiprocessors</searchLink><br /><searchLink fieldCode="DE" term="%22Directory+services+%28Computer+network+technology%29%22">Directory services (Computer network technology)</searchLink><br /><searchLink fieldCode="DE" term="%22Scalability%22">Scalability</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+networks%22">Computer networks</searchLink><br /><searchLink fieldCode="DE" term="%22Energy+consumption%22">Energy consumption</searchLink><br /><searchLink fieldCode="DE" term="%22Static+random+access+memory+chips%22">Static random access memory chips</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: As the number of cores increases in current and future chip-multiprocessor (CMP) generations, coherence protocols must rely on novel hardware structures to scale in terms of performance, power, and area. Systems that use directory information for coherence purposes are currently the most scalable alternative. This paper studies the important differences between the directory behavior of private and shared blocks, which claim for a separate management of both types of blocks at the directory. We propose the PS directory, a two-level directory cache that keeps the reduced number of frequently accessed shared entries in a small and fast first-level cache, namely Shared cache, and uses a larger and slower second-level Private cache to track the large amount of private blocks. Entries in the Private cache do not implement the sharer vector, which allows important silicon area savings. Speed and area reasons suggest the use of eDRAM technology, much denser but slower than SRAM technology, for the Private cache, which in turn brings energy savings. Experimental results for a 16-core CMP show that, compared to a conventional directory, the PS directory improves performance by 14 $$\%$$ while reducing silicon area and energy consumption by 34 and 27 $$\%$$ , respectively. Also, compared to the state-of-the-art Multi-Grain Directory, the PS directory apart from increasing performance, it reduces power by 18.7 $$\%$$ , and provides more scalability in terms of area. [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of Journal of Supercomputing is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1007/s11227-014-1332-5 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 30 StartPage: 2847 Subjects: – SubjectFull: Performance of multiprocessors Type: general – SubjectFull: Directory services (Computer network technology) Type: general – SubjectFull: Scalability Type: general – SubjectFull: Computer networks Type: general – SubjectFull: Energy consumption Type: general – SubjectFull: Static random access memory chips Type: general Titles: – TitleFull: PS directory: a scalable multilevel directory cache for CMPs. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Valls, Joan – PersonEntity: Name: NameFull: Ros, Alberto – PersonEntity: Name: NameFull: Sahuquillo, Julio – PersonEntity: Name: NameFull: Gómez, María IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 08 Text: Aug2015 Type: published Y: 2015 Identifiers: – Type: issn-print Value: 09208542 Numbering: – Type: volume Value: 71 – Type: issue Value: 8 Titles: – TitleFull: Journal of Supercomputing Type: main |
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