Characterization of Single-Event Transient Pulse Quenching among Dummy Gate Isolated Logic Nodes in 65 nm Twin-Well and Triple-Well CMOS Technologies.
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| Title: | Characterization of Single-Event Transient Pulse Quenching among Dummy Gate Isolated Logic Nodes in 65 nm Twin-Well and Triple-Well CMOS Technologies. |
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| Authors: | Jianjun, Chen1, Shuming, Chen1, Yaqing, Chi1, Bin, Liang1 |
| Source: | IEEE Transactions on Nuclear Science. Oct2015 Part 2, Vol. 62 Issue 5b, p2302-2309. 8p. |
| Subjects: | Logic circuits, CMOS memory circuits, Pulse modulation, Charge sharing (Digital electronics), Transient analysis |
| Abstract: | As chip technologies scale down in size, a single high-energy ion strike often affects multiple adjacent logic nodes. The so-called pulse quenching effect, induced by single-event charge sharing collection, has been widely explored in efforts to find mitigation techniques for single-event transients (SETs) or single-event upsets (SEUs), and the dummy gate isolation has been proven to be an efficient layout technique for pulse quenching enhancement. In this paper, the characterization of SET pulse quenching among dummy gate isolated logic nodes is performed in 65 nm twin-well and triple-well CMOS technologies. Four groups of heavy ion experiments are explored for the characterization, and the pulse quenching effect is quantitatively analyzed in detail. The pulse quenching effects show different characteristics in twin-well and triple-well CMOS technologies. [ABSTRACT FROM AUTHOR] |
| Copyright of IEEE Transactions on Nuclear Science is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
| FullText | Text: Availability: 0 |
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| Header | DbId: egs DbLabel: Engineering Source An: 110334342 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: Characterization of Single-Event Transient Pulse Quenching among Dummy Gate Isolated Logic Nodes in 65 nm Twin-Well and Triple-Well CMOS Technologies. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Jianjun%2C+Chen%22">Jianjun, Chen</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Shuming%2C+Chen%22">Shuming, Chen</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Yaqing%2C+Chi%22">Yaqing, Chi</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Bin%2C+Liang%22">Bin, Liang</searchLink><relatesTo>1</relatesTo> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22IEEE+Transactions+on+Nuclear+Science%22">IEEE Transactions on Nuclear Science</searchLink>. Oct2015 Part 2, Vol. 62 Issue 5b, p2302-2309. 8p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Logic+circuits%22">Logic circuits</searchLink><br /><searchLink fieldCode="DE" term="%22CMOS+memory+circuits%22">CMOS memory circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Pulse+modulation%22">Pulse modulation</searchLink><br /><searchLink fieldCode="DE" term="%22Charge+sharing+%28Digital+electronics%29%22">Charge sharing (Digital electronics)</searchLink><br /><searchLink fieldCode="DE" term="%22Transient+analysis%22">Transient analysis</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: As chip technologies scale down in size, a single high-energy ion strike often affects multiple adjacent logic nodes. The so-called pulse quenching effect, induced by single-event charge sharing collection, has been widely explored in efforts to find mitigation techniques for single-event transients (SETs) or single-event upsets (SEUs), and the dummy gate isolation has been proven to be an efficient layout technique for pulse quenching enhancement. In this paper, the characterization of SET pulse quenching among dummy gate isolated logic nodes is performed in 65 nm twin-well and triple-well CMOS technologies. Four groups of heavy ion experiments are explored for the characterization, and the pulse quenching effect is quantitatively analyzed in detail. The pulse quenching effects show different characteristics in twin-well and triple-well CMOS technologies. [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of IEEE Transactions on Nuclear Science is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1109/TNS.2015.2469740 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 8 StartPage: 2302 Subjects: – SubjectFull: Logic circuits Type: general – SubjectFull: CMOS memory circuits Type: general – SubjectFull: Pulse modulation Type: general – SubjectFull: Charge sharing (Digital electronics) Type: general – SubjectFull: Transient analysis Type: general Titles: – TitleFull: Characterization of Single-Event Transient Pulse Quenching among Dummy Gate Isolated Logic Nodes in 65 nm Twin-Well and Triple-Well CMOS Technologies. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Jianjun, Chen – PersonEntity: Name: NameFull: Shuming, Chen – PersonEntity: Name: NameFull: Yaqing, Chi – PersonEntity: Name: NameFull: Bin, Liang IsPartOfRelationships: – BibEntity: Dates: – D: 15 M: 10 Text: Oct2015 Part 2 Type: published Y: 2015 Identifiers: – Type: issn-print Value: 00189499 Numbering: – Type: volume Value: 62 – Type: issue Value: 5b Titles: – TitleFull: IEEE Transactions on Nuclear Science Type: main |
| ResultId | 1 |
