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Reimagining Heterogeneous Computing: A Functional Instruction-Set Architecture Computing Model.

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Bibliographic Details
Title:	Reimagining Heterogeneous Computing: A Functional Instruction-Set Architecture Computing Model.
Authors:	Nemirovsky, Daniel¹, Markovic, Nikola¹, Unsal, Osman¹, Valero, Mateo¹, Cristal, Adrian¹
Source:	IEEE Micro. Sep2015, Vol. 35 Issue 5, p6-14. 9p.
Subjects:	Heterogeneous computing, Computer architecture, Moore's law, Data mapping, Transistors
Abstract:	The relentless push in technology scaling driven by Moore's law has witnessed fantastic gains in the quantities of transistors available on chips. Computer architects have exploited the extra transistors by incorporating several computing cores within a single processor. Heterogeneous processing in particular has become a useful technique for dealing with ever-present power and memory restrictions. Yet, the scope and diversity of current heterogeneous designs remain bounded by the level of functional abstraction specified by conventional instruction-set architectures (ISAs). In this article, the authors demonstrate how the functional abstraction level determines the capability and variety of a processor's functional units and accelerators, thereby restricting its degree of heterogeneity. Combining current heterogeneous techniques with software abstraction concepts, the authors propose a new functional ISA (F-ISA), which raises the functional abstraction level of machine instructions. Using this model to complement existing architectures makes available a wider scope and diversity of functional units and accelerators in order to exploit the ever-increasing transistor densities. Greater heterogeneity can offer advances in terms of object data mapping and execution, resulting in potentially substantial latency, memory footprint, and power/performance gains. [ABSTRACT FROM PUBLISHER]
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Database:	Engineering Source

Description
Abstract:	The relentless push in technology scaling driven by Moore's law has witnessed fantastic gains in the quantities of transistors available on chips. Computer architects have exploited the extra transistors by incorporating several computing cores within a single processor. Heterogeneous processing in particular has become a useful technique for dealing with ever-present power and memory restrictions. Yet, the scope and diversity of current heterogeneous designs remain bounded by the level of functional abstraction specified by conventional instruction-set architectures (ISAs). In this article, the authors demonstrate how the functional abstraction level determines the capability and variety of a processor's functional units and accelerators, thereby restricting its degree of heterogeneity. Combining current heterogeneous techniques with software abstraction concepts, the authors propose a new functional ISA (F-ISA), which raises the functional abstraction level of machine instructions. Using this model to complement existing architectures makes available a wider scope and diversity of functional units and accelerators in order to exploit the ever-increasing transistor densities. Greater heterogeneity can offer advances in terms of object data mapping and execution, resulting in potentially substantial latency, memory footprint, and power/performance gains. [ABSTRACT FROM PUBLISHER]
ISSN:	02721732
DOI:	10.1109/MM.2015.109