Reimagining Heterogeneous Computing: A Functional Instruction-Set Architecture Computing Model.
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| Title: | Reimagining Heterogeneous Computing: A Functional Instruction-Set Architecture Computing Model. |
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| Authors: | Nemirovsky, Daniel1, Markovic, Nikola1, Unsal, Osman1, Valero, Mateo1, Cristal, Adrian1 |
| Source: | IEEE Micro. Sep2015, Vol. 35 Issue 5, p6-14. 9p. |
| Subjects: | Heterogeneous computing, Computer architecture, Moore's law, Data mapping, Transistors |
| Abstract: | The relentless push in technology scaling driven by Moore's law has witnessed fantastic gains in the quantities of transistors available on chips. Computer architects have exploited the extra transistors by incorporating several computing cores within a single processor. Heterogeneous processing in particular has become a useful technique for dealing with ever-present power and memory restrictions. Yet, the scope and diversity of current heterogeneous designs remain bounded by the level of functional abstraction specified by conventional instruction-set architectures (ISAs). In this article, the authors demonstrate how the functional abstraction level determines the capability and variety of a processor's functional units and accelerators, thereby restricting its degree of heterogeneity. Combining current heterogeneous techniques with software abstraction concepts, the authors propose a new functional ISA (F-ISA), which raises the functional abstraction level of machine instructions. Using this model to complement existing architectures makes available a wider scope and diversity of functional units and accelerators in order to exploit the ever-increasing transistor densities. Greater heterogeneity can offer advances in terms of object data mapping and execution, resulting in potentially substantial latency, memory footprint, and power/performance gains. [ABSTRACT FROM PUBLISHER] |
| Copyright of IEEE Micro is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
| FullText | Text: Availability: 0 |
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| Header | DbId: egs DbLabel: Engineering Source An: 110690337 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: Reimagining Heterogeneous Computing: A Functional Instruction-Set Architecture Computing Model. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Nemirovsky%2C+Daniel%22">Nemirovsky, Daniel</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Markovic%2C+Nikola%22">Markovic, Nikola</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Unsal%2C+Osman%22">Unsal, Osman</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Valero%2C+Mateo%22">Valero, Mateo</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Cristal%2C+Adrian%22">Cristal, Adrian</searchLink><relatesTo>1</relatesTo> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22IEEE+Micro%22">IEEE Micro</searchLink>. Sep2015, Vol. 35 Issue 5, p6-14. 9p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Heterogeneous+computing%22">Heterogeneous computing</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+architecture%22">Computer architecture</searchLink><br /><searchLink fieldCode="DE" term="%22Moore's+law%22">Moore's law</searchLink><br /><searchLink fieldCode="DE" term="%22Data+mapping%22">Data mapping</searchLink><br /><searchLink fieldCode="DE" term="%22Transistors%22">Transistors</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: The relentless push in technology scaling driven by Moore's law has witnessed fantastic gains in the quantities of transistors available on chips. Computer architects have exploited the extra transistors by incorporating several computing cores within a single processor. Heterogeneous processing in particular has become a useful technique for dealing with ever-present power and memory restrictions. Yet, the scope and diversity of current heterogeneous designs remain bounded by the level of functional abstraction specified by conventional instruction-set architectures (ISAs). In this article, the authors demonstrate how the functional abstraction level determines the capability and variety of a processor's functional units and accelerators, thereby restricting its degree of heterogeneity. Combining current heterogeneous techniques with software abstraction concepts, the authors propose a new functional ISA (F-ISA), which raises the functional abstraction level of machine instructions. Using this model to complement existing architectures makes available a wider scope and diversity of functional units and accelerators in order to exploit the ever-increasing transistor densities. Greater heterogeneity can offer advances in terms of object data mapping and execution, resulting in potentially substantial latency, memory footprint, and power/performance gains. [ABSTRACT FROM PUBLISHER] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of IEEE Micro is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1109/MM.2015.109 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 9 StartPage: 6 Subjects: – SubjectFull: Heterogeneous computing Type: general – SubjectFull: Computer architecture Type: general – SubjectFull: Moore's law Type: general – SubjectFull: Data mapping Type: general – SubjectFull: Transistors Type: general Titles: – TitleFull: Reimagining Heterogeneous Computing: A Functional Instruction-Set Architecture Computing Model. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Nemirovsky, Daniel – PersonEntity: Name: NameFull: Markovic, Nikola – PersonEntity: Name: NameFull: Unsal, Osman – PersonEntity: Name: NameFull: Valero, Mateo – PersonEntity: Name: NameFull: Cristal, Adrian IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 09 Text: Sep2015 Type: published Y: 2015 Identifiers: – Type: issn-print Value: 02721732 Numbering: – Type: volume Value: 35 – Type: issue Value: 5 Titles: – TitleFull: IEEE Micro Type: main |
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