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Virtual Prototyper (ViPro): An SRAM Design Tool for Yield Constrained Optimization.

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Bibliographic Details
Title: Virtual Prototyper (ViPro): An SRAM Design Tool for Yield Constrained Optimization.
Authors: Boley, Jim1, Beshay, Peter1, Calhoun, Benton1
Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. Dec2015, Vol. 23 Issue 12, p3109-3113. 5p.
Subjects: Static random access memory chips, Integrated memory circuits, Simulation methods & models, Energy consumption, Random access memory
Abstract: This brief presents a tool for optimizing the energy and delay (E/D) of static RAM designs to meet a specific die yield constraint. This allows the tool to account for the effects of process variation and to trade off yield with performance and energy. To accomplish this, we use a combination of simulation and modeling techniques to determine the minimum wordline (WL) pulsewidth required for both the read and write operations to meet a user-specified die yield. The use of a hierarchical model enables us to calculate the E/D of a full macro that is margined to meet a specific die yield. By sweeping across the possible design space, we are able to identify Pareto optimal designs. The tool structure described in this brief allows comparison across different array topologies, process technologies, and circuit choices including assist methods. Using this tool, we find that adding a WL boosting scheme results in an overall energy savings, despite the overhead of using a charge pump circuit, due to an improved read delay distribution. [ABSTRACT FROM AUTHOR]
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Database: Engineering Source
Description
Abstract:This brief presents a tool for optimizing the energy and delay (E/D) of static RAM designs to meet a specific die yield constraint. This allows the tool to account for the effects of process variation and to trade off yield with performance and energy. To accomplish this, we use a combination of simulation and modeling techniques to determine the minimum wordline (WL) pulsewidth required for both the read and write operations to meet a user-specified die yield. The use of a hierarchical model enables us to calculate the E/D of a full macro that is margined to meet a specific die yield. By sweeping across the possible design space, we are able to identify Pareto optimal designs. The tool structure described in this brief allows comparison across different array topologies, process technologies, and circuit choices including assist methods. Using this tool, we find that adding a WL boosting scheme results in an overall energy savings, despite the overhead of using a charge pump circuit, due to an improved read delay distribution. [ABSTRACT FROM AUTHOR]
ISSN:10638210
DOI:10.1109/TVLSI.2014.2385832