APA (7th ed.) Citation

Boley, J., Beshay, P., & Calhoun, B. (2015). Virtual Prototyper (ViPro): An SRAM Design Tool for Yield Constrained Optimization. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 23(12), 3109. https://doi.org/10.1109/TVLSI.2014.2385832

Chicago Style (17th ed.) Citation

Boley, Jim, Peter Beshay, and Benton Calhoun. "Virtual Prototyper (ViPro): An SRAM Design Tool for Yield Constrained Optimization." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23, no. 12 (2015): 3109. https://doi.org/10.1109/TVLSI.2014.2385832.

MLA (9th ed.) Citation

Boley, Jim, et al. "Virtual Prototyper (ViPro): An SRAM Design Tool for Yield Constrained Optimization." IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 23, no. 12, 2015, p. 3109, https://doi.org/10.1109/TVLSI.2014.2385832.