Virtual Prototyper (ViPro): An SRAM Design Tool for Yield Constrained Optimization.
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| Title: | Virtual Prototyper (ViPro): An SRAM Design Tool for Yield Constrained Optimization. |
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| Authors: | Boley, Jim1, Beshay, Peter1, Calhoun, Benton1 |
| Source: | IEEE Transactions on Very Large Scale Integration (VLSI) Systems. Dec2015, Vol. 23 Issue 12, p3109-3113. 5p. |
| Subjects: | Static random access memory chips, Integrated memory circuits, Simulation methods & models, Energy consumption, Random access memory |
| Abstract: | This brief presents a tool for optimizing the energy and delay (E/D) of static RAM designs to meet a specific die yield constraint. This allows the tool to account for the effects of process variation and to trade off yield with performance and energy. To accomplish this, we use a combination of simulation and modeling techniques to determine the minimum wordline (WL) pulsewidth required for both the read and write operations to meet a user-specified die yield. The use of a hierarchical model enables us to calculate the E/D of a full macro that is margined to meet a specific die yield. By sweeping across the possible design space, we are able to identify Pareto optimal designs. The tool structure described in this brief allows comparison across different array topologies, process technologies, and circuit choices including assist methods. Using this tool, we find that adding a WL boosting scheme results in an overall energy savings, despite the overhead of using a charge pump circuit, due to an improved read delay distribution. [ABSTRACT FROM AUTHOR] |
| Copyright of IEEE Transactions on Very Large Scale Integration (VLSI) Systems is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
| FullText | Text: Availability: 0 |
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| Header | DbId: egs DbLabel: Engineering Source An: 111173321 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: Virtual Prototyper (ViPro): An SRAM Design Tool for Yield Constrained Optimization. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Boley%2C+Jim%22">Boley, Jim</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Beshay%2C+Peter%22">Beshay, Peter</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Calhoun%2C+Benton%22">Calhoun, Benton</searchLink><relatesTo>1</relatesTo> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22IEEE+Transactions+on+Very+Large+Scale+Integration+%28VLSI%29+Systems%22">IEEE Transactions on Very Large Scale Integration (VLSI) Systems</searchLink>. Dec2015, Vol. 23 Issue 12, p3109-3113. 5p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Static+random+access+memory+chips%22">Static random access memory chips</searchLink><br /><searchLink fieldCode="DE" term="%22Integrated+memory+circuits%22">Integrated memory circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Simulation+methods+%26+models%22">Simulation methods & models</searchLink><br /><searchLink fieldCode="DE" term="%22Energy+consumption%22">Energy consumption</searchLink><br /><searchLink fieldCode="DE" term="%22Random+access+memory%22">Random access memory</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: This brief presents a tool for optimizing the energy and delay (E/D) of static RAM designs to meet a specific die yield constraint. This allows the tool to account for the effects of process variation and to trade off yield with performance and energy. To accomplish this, we use a combination of simulation and modeling techniques to determine the minimum wordline (WL) pulsewidth required for both the read and write operations to meet a user-specified die yield. The use of a hierarchical model enables us to calculate the E/D of a full macro that is margined to meet a specific die yield. By sweeping across the possible design space, we are able to identify Pareto optimal designs. The tool structure described in this brief allows comparison across different array topologies, process technologies, and circuit choices including assist methods. Using this tool, we find that adding a WL boosting scheme results in an overall energy savings, despite the overhead of using a charge pump circuit, due to an improved read delay distribution. [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of IEEE Transactions on Very Large Scale Integration (VLSI) Systems is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1109/TVLSI.2014.2385832 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 5 StartPage: 3109 Subjects: – SubjectFull: Static random access memory chips Type: general – SubjectFull: Integrated memory circuits Type: general – SubjectFull: Simulation methods & models Type: general – SubjectFull: Energy consumption Type: general – SubjectFull: Random access memory Type: general Titles: – TitleFull: Virtual Prototyper (ViPro): An SRAM Design Tool for Yield Constrained Optimization. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Boley, Jim – PersonEntity: Name: NameFull: Beshay, Peter – PersonEntity: Name: NameFull: Calhoun, Benton IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 12 Text: Dec2015 Type: published Y: 2015 Identifiers: – Type: issn-print Value: 10638210 Numbering: – Type: volume Value: 23 – Type: issue Value: 12 Titles: – TitleFull: IEEE Transactions on Very Large Scale Integration (VLSI) Systems Type: main |
| ResultId | 1 |
