Bibliographic Details
| Title: |
A Dynamically Reconfigurable Multi-ASIP Architecture for Multistandard and Multimode Turbo Decoding. |
| Authors: |
Lapotre, Vianney1, Gogniat, Guy1, Diguet, Jean-Philippe1, Murugappa, Purushotham2, Baghdadi, Amer2, Hubner, Michael3 |
| Source: |
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. Jan2016, Vol. 24 Issue 1, p383-387. 5p. |
| Subjects: |
Application-specific instruction-set processors, Turbo codes, Wireless communications, Multiprocessors, Decoding algorithms, Channel coding |
| Abstract: |
The multiplication of wireless communication standards is introducing the need of flexible and reconfigurable multistandard baseband receivers. In this context, multiprocessor turbo decoders have been recently developed in order to support the increasing flexibility and throughput requirements of emerging applications. However, these solutions do not sufficiently address reconfiguration performance issues, which can be a limiting factor in the future. This brief presents the design of a reconfigurable multiprocessor architecture for turbo decoding achieving very fast reconfiguration without compromising the decoding performances. [ABSTRACT FROM PUBLISHER] |
|
Copyright of IEEE Transactions on Very Large Scale Integration (VLSI) Systems is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) |
| Database: |
Engineering Source |
