View in EDS

A Dynamically Reconfigurable Multi-ASIP Architecture for Multistandard and Multimode Turbo Decoding.

Saved in:
Bibliographic Details
Title: A Dynamically Reconfigurable Multi-ASIP Architecture for Multistandard and Multimode Turbo Decoding.
Authors: Lapotre, Vianney1, Gogniat, Guy1, Diguet, Jean-Philippe1, Murugappa, Purushotham2, Baghdadi, Amer2, Hubner, Michael3
Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. Jan2016, Vol. 24 Issue 1, p383-387. 5p.
Subjects: Application-specific instruction-set processors, Turbo codes, Wireless communications, Multiprocessors, Decoding algorithms, Channel coding
Abstract: The multiplication of wireless communication standards is introducing the need of flexible and reconfigurable multistandard baseband receivers. In this context, multiprocessor turbo decoders have been recently developed in order to support the increasing flexibility and throughput requirements of emerging applications. However, these solutions do not sufficiently address reconfiguration performance issues, which can be a limiting factor in the future. This brief presents the design of a reconfigurable multiprocessor architecture for turbo decoding achieving very fast reconfiguration without compromising the decoding performances. [ABSTRACT FROM PUBLISHER]
Copyright of IEEE Transactions on Very Large Scale Integration (VLSI) Systems is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
Database: Engineering Source
FullText Text:
  Availability: 0
Header DbId: egs
DbLabel: Engineering Source
An: 111983275
AccessLevel: 6
PubType: Academic Journal
PubTypeId: academicJournal
PreciseRelevancyScore: 0
IllustrationInfo
Items – Name: Title
  Label: Title
  Group: Ti
  Data: A Dynamically Reconfigurable Multi-ASIP Architecture for Multistandard and Multimode Turbo Decoding.
– Name: Author
  Label: Authors
  Group: Au
  Data: <searchLink fieldCode="AR" term="%22Lapotre%2C+Vianney%22">Lapotre, Vianney</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Gogniat%2C+Guy%22">Gogniat, Guy</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Diguet%2C+Jean-Philippe%22">Diguet, Jean-Philippe</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Murugappa%2C+Purushotham%22">Murugappa, Purushotham</searchLink><relatesTo>2</relatesTo><br /><searchLink fieldCode="AR" term="%22Baghdadi%2C+Amer%22">Baghdadi, Amer</searchLink><relatesTo>2</relatesTo><br /><searchLink fieldCode="AR" term="%22Hubner%2C+Michael%22">Hubner, Michael</searchLink><relatesTo>3</relatesTo>
– Name: TitleSource
  Label: Source
  Group: Src
  Data: <searchLink fieldCode="JN" term="%22IEEE+Transactions+on+Very+Large+Scale+Integration+%28VLSI%29+Systems%22">IEEE Transactions on Very Large Scale Integration (VLSI) Systems</searchLink>. Jan2016, Vol. 24 Issue 1, p383-387. 5p.
– Name: Subject
  Label: Subjects
  Group: Su
  Data: <searchLink fieldCode="DE" term="%22Application-specific+instruction-set+processors%22">Application-specific instruction-set processors</searchLink><br /><searchLink fieldCode="DE" term="%22Turbo+codes%22">Turbo codes</searchLink><br /><searchLink fieldCode="DE" term="%22Wireless+communications%22">Wireless communications</searchLink><br /><searchLink fieldCode="DE" term="%22Multiprocessors%22">Multiprocessors</searchLink><br /><searchLink fieldCode="DE" term="%22Decoding+algorithms%22">Decoding algorithms</searchLink><br /><searchLink fieldCode="DE" term="%22Channel+coding%22">Channel coding</searchLink>
– Name: Abstract
  Label: Abstract
  Group: Ab
  Data: The multiplication of wireless communication standards is introducing the need of flexible and reconfigurable multistandard baseband receivers. In this context, multiprocessor turbo decoders have been recently developed in order to support the increasing flexibility and throughput requirements of emerging applications. However, these solutions do not sufficiently address reconfiguration performance issues, which can be a limiting factor in the future. This brief presents the design of a reconfigurable multiprocessor architecture for turbo decoding achieving very fast reconfiguration without compromising the decoding performances. [ABSTRACT FROM PUBLISHER]
– Name: AbstractSuppliedCopyright
  Label:
  Group: Ab
  Data: <i>Copyright of IEEE Transactions on Very Large Scale Integration (VLSI) Systems is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
PLink https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=egs&AN=111983275
RecordInfo BibRecord:
  BibEntity:
    Identifiers:
      – Type: doi
        Value: 10.1109/TVLSI.2015.2396941
    Languages:
      – Code: eng
        Text: English
    PhysicalDescription:
      Pagination:
        PageCount: 5
        StartPage: 383
    Subjects:
      – SubjectFull: Application-specific instruction-set processors
        Type: general
      – SubjectFull: Turbo codes
        Type: general
      – SubjectFull: Wireless communications
        Type: general
      – SubjectFull: Multiprocessors
        Type: general
      – SubjectFull: Decoding algorithms
        Type: general
      – SubjectFull: Channel coding
        Type: general
    Titles:
      – TitleFull: A Dynamically Reconfigurable Multi-ASIP Architecture for Multistandard and Multimode Turbo Decoding.
        Type: main
  BibRelationships:
    HasContributorRelationships:
      – PersonEntity:
          Name:
            NameFull: Lapotre, Vianney
      – PersonEntity:
          Name:
            NameFull: Gogniat, Guy
      – PersonEntity:
          Name:
            NameFull: Diguet, Jean-Philippe
      – PersonEntity:
          Name:
            NameFull: Murugappa, Purushotham
      – PersonEntity:
          Name:
            NameFull: Baghdadi, Amer
      – PersonEntity:
          Name:
            NameFull: Hubner, Michael
    IsPartOfRelationships:
      – BibEntity:
          Dates:
            – D: 01
              M: 01
              Text: Jan2016
              Type: published
              Y: 2016
          Identifiers:
            – Type: issn-print
              Value: 10638210
          Numbering:
            – Type: volume
              Value: 24
            – Type: issue
              Value: 1
          Titles:
            – TitleFull: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
              Type: main
ResultId 1