Bibliographic Details
| Title: |
A SUC-Based Full-Binary 6-bit 3.1-GS/s 17.7-mW Current-Steering DAC in 0.038 mm ^2. |
| Authors: |
Kim, Si-Nai1, Kim, Mee-Ran1, Sung, Ba-Ro-Saim1, Kang, Hyun-Wook1, Cho, Min-Hyung2, Ryu, Seung-Tak1 |
| Source: |
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. Feb2016, Vol. 24 Issue 2, p794-798. 5p. |
| Subjects: |
Digital-to-analog converters, Electric current converters, Electric circuit design & construction, Electric power consumption, Nyquist diagram |
| Abstract: |
A 6-bit full-binary compact and low-power current-steering digital-to-analog converter (DAC) designed for 60-GHz Wireless Personal Area Network applications is presented. The closely located circuit components based on the stacked unit cell minimize the parasitic capacitance and enhance the high-frequency dynamic linearity. The proposed binary structure realizes a compact DAC by eliminating the need for additional circuits, such as thermometer decoders, and thus reduces power consumption. A prototype 6-bit 3.1-GS/s full-binary DAC was fabricated in a 90-nm CMOS process. The DAC exhibits a spurious-free dynamic range of >37.2 dB up to 3.1 GS/s over the Nyquist input. The chip consumes 17.7 mW of power and occupies 0.038 mm ^2 of core size. [ABSTRACT FROM AUTHOR] |
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| Database: |
Engineering Source |
