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A SUC-Based Full-Binary 6-bit 3.1-GS/s 17.7-mW Current-Steering DAC in 0.038 mm ^2.

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Title: A SUC-Based Full-Binary 6-bit 3.1-GS/s 17.7-mW Current-Steering DAC in 0.038 mm ^2.
Authors: Kim, Si-Nai1, Kim, Mee-Ran1, Sung, Ba-Ro-Saim1, Kang, Hyun-Wook1, Cho, Min-Hyung2, Ryu, Seung-Tak1
Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. Feb2016, Vol. 24 Issue 2, p794-798. 5p.
Subjects: Digital-to-analog converters, Electric current converters, Electric circuit design & construction, Electric power consumption, Nyquist diagram
Abstract: A 6-bit full-binary compact and low-power current-steering digital-to-analog converter (DAC) designed for 60-GHz Wireless Personal Area Network applications is presented. The closely located circuit components based on the stacked unit cell minimize the parasitic capacitance and enhance the high-frequency dynamic linearity. The proposed binary structure realizes a compact DAC by eliminating the need for additional circuits, such as thermometer decoders, and thus reduces power consumption. A prototype 6-bit 3.1-GS/s full-binary DAC was fabricated in a 90-nm CMOS process. The DAC exhibits a spurious-free dynamic range of >37.2 dB up to 3.1 GS/s over the Nyquist input. The chip consumes 17.7 mW of power and occupies 0.038 mm ^2 of core size. [ABSTRACT FROM AUTHOR]
Copyright of IEEE Transactions on Very Large Scale Integration (VLSI) Systems is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
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  Data: A SUC-Based Full-Binary 6-bit 3.1-GS/s 17.7-mW Current-Steering DAC in 0.038 mm ^2.
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  Data: <searchLink fieldCode="DE" term="%22Digital-to-analog+converters%22">Digital-to-analog converters</searchLink><br /><searchLink fieldCode="DE" term="%22Electric+current+converters%22">Electric current converters</searchLink><br /><searchLink fieldCode="DE" term="%22Electric+circuit+design+%26+construction%22">Electric circuit design & construction</searchLink><br /><searchLink fieldCode="DE" term="%22Electric+power+consumption%22">Electric power consumption</searchLink><br /><searchLink fieldCode="DE" term="%22Nyquist+diagram%22">Nyquist diagram</searchLink>
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  Data: A 6-bit full-binary compact and low-power current-steering digital-to-analog converter (DAC) designed for 60-GHz Wireless Personal Area Network applications is presented. The closely located circuit components based on the stacked unit cell minimize the parasitic capacitance and enhance the high-frequency dynamic linearity. The proposed binary structure realizes a compact DAC by eliminating the need for additional circuits, such as thermometer decoders, and thus reduces power consumption. A prototype 6-bit 3.1-GS/s full-binary DAC was fabricated in a 90-nm CMOS process. The DAC exhibits a spurious-free dynamic range of >37.2 dB up to 3.1 GS/s over the Nyquist input. The chip consumes 17.7 mW of power and occupies 0.038 mm ^2 of core size. [ABSTRACT FROM AUTHOR]
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  Data: <i>Copyright of IEEE Transactions on Very Large Scale Integration (VLSI) Systems is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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