Bibliographic Details
| Title: |
Design for Testability of Sleep Convention Logic. |
| Authors: |
Parsan, Farhad A.1, Smith, Scott C.2, Al-Assadi, Waleed K.3 |
| Source: |
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. Feb2016, Vol. 24 Issue 2, p743-753. 11p. |
| Subjects: |
Systems on a chip, Systems on a chip testing, Logic circuits, Industrial costs, Fault tolerance (Engineering) |
| Abstract: |
Testability is a major concern in industry for today’s complex system-on-chip design. Design-for-testability (DFT) techniques are essential for any logic style, including asynchronous logic styles in order to reduce the test cost. Sleep convention logic (SCL) is a new promising asynchronous logic style that is based on the more well-known asynchronous logic style NULL convention logic (NCL). In contrast to the NCL, there are currently no design for testability methodologies existing for the SCL. The aim of this paper is to analyze the various faults within SCL pipelines and propose a scan-based DFT methodology to make the SCL testable. The proposed DFT methodology is then validated through a number of experiments, showing that the methodology provides a high test coverage (>99%). The complete DFT methodology as well as the scan chain and scan cell design are presented. [ABSTRACT FROM AUTHOR] |
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| Database: |
Engineering Source |
