A High-Density Metal-Fuse Technology Featuring a 1.6 V Programmable Low-Voltage Bit Cell With Integrated 1 V Charge Pumps in 22 nm Tri-Gate CMOS.

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Bibliographic Details
Title: A High-Density Metal-Fuse Technology Featuring a 1.6 V Programmable Low-Voltage Bit Cell With Integrated 1 V Charge Pumps in 22 nm Tri-Gate CMOS.
Authors: Kulkarni, Sarvesh H.1, Chen, Zhanping1, Srinivasan, Balaji2, Pedersen, Brian3, Bhattacharya, Uddalak1, Zhang, Kevin1
Source: IEEE Journal of Solid-State Circuits. Apr2016, Vol. 51 Issue 4, p1003-1008. 6p.
Subjects: Programmable read-only memory, CMOS integrated circuits, Integrated memory circuits, Programmable circuits, Integrated circuit design
Abstract: The first metal-fuse technology in 22 nm tri-gate high-k metal-gate CMOS technology is presented. The memory technology offerings in high-volume manufacturing include a 2.05\;\upmu \textm^2 2.2 V programmable high-density and a 16.4\,\upmu \textm^2 1.6 V programmable low-voltage (LV) 1T1R bit cell. The LV operability of the technology allows the fuse arrays to be coupled with power delivery circuits operating at standard logic voltage levels. A charge pump voltage doubler operating on a 1 V voltage rail is demonstrated in this paper with healthy fusing yield. [ABSTRACT FROM PUBLISHER]
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Description
Abstract:The first metal-fuse technology in 22 nm tri-gate high-k metal-gate CMOS technology is presented. The memory technology offerings in high-volume manufacturing include a 2.05\;\upmu \textm^2 2.2 V programmable high-density and a 16.4\,\upmu \textm^2 1.6 V programmable low-voltage (LV) 1T1R bit cell. The LV operability of the technology allows the fuse arrays to be coupled with power delivery circuits operating at standard logic voltage levels. A charge pump voltage doubler operating on a 1 V voltage rail is demonstrated in this paper with healthy fusing yield. [ABSTRACT FROM PUBLISHER]
ISSN:00189200
DOI:10.1109/JSSC.2015.2507786