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A Low-Cost, Radiation-Hardened Method for Pipeline Protection in Microprocessors.

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Title: A Low-Cost, Radiation-Hardened Method for Pipeline Protection in Microprocessors.
Authors: Lin, Yang1, Zwolinski, Mark1, Halak, Basel1
Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. May2016, Vol. 24 Issue 5, p1688-1701. 14p.
Subjects: Microprocessor performance, Semiconductor technology, Semiconductor devices, Soft errors, Error rates
Abstract: The aggressive scaling of semiconductor technology has significantly increased the radiation-induced soft-error rate in modern microprocessors. Meanwhile, due to the increasing complexity of modern processor pipelines and the limited error-tolerance capabilities that previous radiation hardening techniques can provide, the existing pipeline protection mechanisms cannot achieve complete protection. This paper proposes a complete and cost-effective pipeline protection mechanism using a self-checking architecture. The radiation-hardened pipeline is achieved by incorporating soft-error- and timing-error-tolerant flip-flop (SETTOFF)-based self-checking cells into the sequential cells of the pipeline. A replay recovery mechanism is also developed at the architectural level to recover the detected errors. The proposed pipeline protection technique is implemented in an OpenRISC microprocessor in a 65-nm technology. A gate-level transient fault-injection and analysis technique is used to evaluate the error-tolerance capability of the proposed hardened pipeline design. The results show that compared with the techniques such as triple modular redundancy, the SETTOFF-based self-checking technique requires over 30% less area and 80% less power overheads. Meanwhile, the error-tolerant and self-checking capabilities of the register allow the proposed pipeline protection technique to provide a noticeably higher level of reliability for different parts of the pipeline compared with the previous pipeline protection techniques. [ABSTRACT FROM PUBLISHER]
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Database: Engineering Source
Description
Abstract:The aggressive scaling of semiconductor technology has significantly increased the radiation-induced soft-error rate in modern microprocessors. Meanwhile, due to the increasing complexity of modern processor pipelines and the limited error-tolerance capabilities that previous radiation hardening techniques can provide, the existing pipeline protection mechanisms cannot achieve complete protection. This paper proposes a complete and cost-effective pipeline protection mechanism using a self-checking architecture. The radiation-hardened pipeline is achieved by incorporating soft-error- and timing-error-tolerant flip-flop (SETTOFF)-based self-checking cells into the sequential cells of the pipeline. A replay recovery mechanism is also developed at the architectural level to recover the detected errors. The proposed pipeline protection technique is implemented in an OpenRISC microprocessor in a 65-nm technology. A gate-level transient fault-injection and analysis technique is used to evaluate the error-tolerance capability of the proposed hardened pipeline design. The results show that compared with the techniques such as triple modular redundancy, the SETTOFF-based self-checking technique requires over 30% less area and 80% less power overheads. Meanwhile, the error-tolerant and self-checking capabilities of the register allow the proposed pipeline protection technique to provide a noticeably higher level of reliability for different parts of the pipeline compared with the previous pipeline protection techniques. [ABSTRACT FROM PUBLISHER]
ISSN:10638210
DOI:10.1109/TVLSI.2015.2475167