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A Low-Cost, Radiation-Hardened Method for Pipeline Protection in Microprocessors.

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Title: A Low-Cost, Radiation-Hardened Method for Pipeline Protection in Microprocessors.
Authors: Lin, Yang1, Zwolinski, Mark1, Halak, Basel1
Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. May2016, Vol. 24 Issue 5, p1688-1701. 14p.
Subjects: Microprocessor performance, Semiconductor technology, Semiconductor devices, Soft errors, Error rates
Abstract: The aggressive scaling of semiconductor technology has significantly increased the radiation-induced soft-error rate in modern microprocessors. Meanwhile, due to the increasing complexity of modern processor pipelines and the limited error-tolerance capabilities that previous radiation hardening techniques can provide, the existing pipeline protection mechanisms cannot achieve complete protection. This paper proposes a complete and cost-effective pipeline protection mechanism using a self-checking architecture. The radiation-hardened pipeline is achieved by incorporating soft-error- and timing-error-tolerant flip-flop (SETTOFF)-based self-checking cells into the sequential cells of the pipeline. A replay recovery mechanism is also developed at the architectural level to recover the detected errors. The proposed pipeline protection technique is implemented in an OpenRISC microprocessor in a 65-nm technology. A gate-level transient fault-injection and analysis technique is used to evaluate the error-tolerance capability of the proposed hardened pipeline design. The results show that compared with the techniques such as triple modular redundancy, the SETTOFF-based self-checking technique requires over 30% less area and 80% less power overheads. Meanwhile, the error-tolerant and self-checking capabilities of the register allow the proposed pipeline protection technique to provide a noticeably higher level of reliability for different parts of the pipeline compared with the previous pipeline protection techniques. [ABSTRACT FROM PUBLISHER]
Copyright of IEEE Transactions on Very Large Scale Integration (VLSI) Systems is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
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  Data: A Low-Cost, Radiation-Hardened Method for Pipeline Protection in Microprocessors.
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  Data: <searchLink fieldCode="AR" term="%22Lin%2C+Yang%22">Lin, Yang</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Zwolinski%2C+Mark%22">Zwolinski, Mark</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Halak%2C+Basel%22">Halak, Basel</searchLink><relatesTo>1</relatesTo>
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  Data: <searchLink fieldCode="DE" term="%22Microprocessor+performance%22">Microprocessor performance</searchLink><br /><searchLink fieldCode="DE" term="%22Semiconductor+technology%22">Semiconductor technology</searchLink><br /><searchLink fieldCode="DE" term="%22Semiconductor+devices%22">Semiconductor devices</searchLink><br /><searchLink fieldCode="DE" term="%22Soft+errors%22">Soft errors</searchLink><br /><searchLink fieldCode="DE" term="%22Error+rates%22">Error rates</searchLink>
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  Data: The aggressive scaling of semiconductor technology has significantly increased the radiation-induced soft-error rate in modern microprocessors. Meanwhile, due to the increasing complexity of modern processor pipelines and the limited error-tolerance capabilities that previous radiation hardening techniques can provide, the existing pipeline protection mechanisms cannot achieve complete protection. This paper proposes a complete and cost-effective pipeline protection mechanism using a self-checking architecture. The radiation-hardened pipeline is achieved by incorporating soft-error- and timing-error-tolerant flip-flop (SETTOFF)-based self-checking cells into the sequential cells of the pipeline. A replay recovery mechanism is also developed at the architectural level to recover the detected errors. The proposed pipeline protection technique is implemented in an OpenRISC microprocessor in a 65-nm technology. A gate-level transient fault-injection and analysis technique is used to evaluate the error-tolerance capability of the proposed hardened pipeline design. The results show that compared with the techniques such as triple modular redundancy, the SETTOFF-based self-checking technique requires over 30% less area and 80% less power overheads. Meanwhile, the error-tolerant and self-checking capabilities of the register allow the proposed pipeline protection technique to provide a noticeably higher level of reliability for different parts of the pipeline compared with the previous pipeline protection techniques. [ABSTRACT FROM PUBLISHER]
– Name: AbstractSuppliedCopyright
  Label:
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  Data: <i>Copyright of IEEE Transactions on Very Large Scale Integration (VLSI) Systems is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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        Value: 10.1109/TVLSI.2015.2475167
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        Text: English
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        Type: general
      – SubjectFull: Semiconductor technology
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      – SubjectFull: Semiconductor devices
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      – SubjectFull: Soft errors
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      – SubjectFull: Error rates
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              Text: May2016
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