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Minimal Buffer Insertion Based Low Power Clock Tree Synthesis for 3D Integrated Circuits.

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Bibliographic Details
Title: Minimal Buffer Insertion Based Low Power Clock Tree Synthesis for 3D Integrated Circuits.
Authors: Sumanth Kumar, Kamineni1, Reuben, John2
Source: Journal of Circuits, Systems & Computers. Nov2016, Vol. 25 Issue 11, p-1. 17p.
Subjects: Clock distribution networks, Integrated circuits, Complementary metal oxide semiconductors, Energy dissipation, Buffer storage (Computer science), Through-silicon via, Algorithms
Abstract: Three-Dimensional (3D) Integrated Circuits (ICs) offers integrating capabilities of 'More than Moore' while overcoming CMOS scaling limitations, providing the advantages of low power, high performance and reduced costs. The design of the Clock Distribution Network (CDN) for a 3D IC has to be done meticulously to guarantee reliable operation. In the design of the CDN, clock buffers are crucial units that affect the clock skew, slew and power dissipated by the clock tree. In this paper, we propose a two-stage buffering technique that inserts clock buffers for slew control and skew minimization. Such a buffering technique decreases the number of buffers and power dissipated in the clock tree when compared to previous works which were inserting buffers primarily for slew control. We incorporate the proposed buffering technique into the 3D clock tree synthesis algorithm of previous work and evaluate the performance of the clock tree for both single Through-Silicon Vias (TSV) and mutiple TSV approach. When evaluated on IBM benchmarks (r1-r5), our buffering technique results in 25-28% reduction in buffer count and 25-29% reduction in power for single TSV-based 3D CDN. For multi-TSV approach, the performance of our work is even better:around 31-38% reduction in buffer count and 32-39% reduction in power. [ABSTRACT FROM AUTHOR]
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Database: Engineering Source
Description
Abstract:Three-Dimensional (3D) Integrated Circuits (ICs) offers integrating capabilities of 'More than Moore' while overcoming CMOS scaling limitations, providing the advantages of low power, high performance and reduced costs. The design of the Clock Distribution Network (CDN) for a 3D IC has to be done meticulously to guarantee reliable operation. In the design of the CDN, clock buffers are crucial units that affect the clock skew, slew and power dissipated by the clock tree. In this paper, we propose a two-stage buffering technique that inserts clock buffers for slew control and skew minimization. Such a buffering technique decreases the number of buffers and power dissipated in the clock tree when compared to previous works which were inserting buffers primarily for slew control. We incorporate the proposed buffering technique into the 3D clock tree synthesis algorithm of previous work and evaluate the performance of the clock tree for both single Through-Silicon Vias (TSV) and mutiple TSV approach. When evaluated on IBM benchmarks (r1-r5), our buffering technique results in 25-28% reduction in buffer count and 25-29% reduction in power for single TSV-based 3D CDN. For multi-TSV approach, the performance of our work is even better:around 31-38% reduction in buffer count and 32-39% reduction in power. [ABSTRACT FROM AUTHOR]
ISSN:02181266
DOI:10.1142/S0218126616501425