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Minimal Buffer Insertion Based Low Power Clock Tree Synthesis for 3D Integrated Circuits.

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Title: Minimal Buffer Insertion Based Low Power Clock Tree Synthesis for 3D Integrated Circuits.
Authors: Sumanth Kumar, Kamineni1, Reuben, John2
Source: Journal of Circuits, Systems & Computers. Nov2016, Vol. 25 Issue 11, p-1. 17p.
Subjects: Clock distribution networks, Integrated circuits, Complementary metal oxide semiconductors, Energy dissipation, Buffer storage (Computer science), Through-silicon via, Algorithms
Abstract: Three-Dimensional (3D) Integrated Circuits (ICs) offers integrating capabilities of 'More than Moore' while overcoming CMOS scaling limitations, providing the advantages of low power, high performance and reduced costs. The design of the Clock Distribution Network (CDN) for a 3D IC has to be done meticulously to guarantee reliable operation. In the design of the CDN, clock buffers are crucial units that affect the clock skew, slew and power dissipated by the clock tree. In this paper, we propose a two-stage buffering technique that inserts clock buffers for slew control and skew minimization. Such a buffering technique decreases the number of buffers and power dissipated in the clock tree when compared to previous works which were inserting buffers primarily for slew control. We incorporate the proposed buffering technique into the 3D clock tree synthesis algorithm of previous work and evaluate the performance of the clock tree for both single Through-Silicon Vias (TSV) and mutiple TSV approach. When evaluated on IBM benchmarks (r1-r5), our buffering technique results in 25-28% reduction in buffer count and 25-29% reduction in power for single TSV-based 3D CDN. For multi-TSV approach, the performance of our work is even better:around 31-38% reduction in buffer count and 32-39% reduction in power. [ABSTRACT FROM AUTHOR]
Copyright of Journal of Circuits, Systems & Computers is the property of World Scientific Publishing Company and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
Database: Engineering Source
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DbLabel: Engineering Source
An: 117760808
AccessLevel: 6
PubType: Academic Journal
PubTypeId: academicJournal
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IllustrationInfo
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  Data: Minimal Buffer Insertion Based Low Power Clock Tree Synthesis for 3D Integrated Circuits.
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  Data: <searchLink fieldCode="AR" term="%22Sumanth+Kumar%2C+Kamineni%22">Sumanth Kumar, Kamineni</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Reuben%2C+John%22">Reuben, John</searchLink><relatesTo>2</relatesTo>
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  Data: <searchLink fieldCode="JN" term="%22Journal+of+Circuits%2C+Systems+%26+Computers%22">Journal of Circuits, Systems & Computers</searchLink>. Nov2016, Vol. 25 Issue 11, p-1. 17p.
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  Data: <searchLink fieldCode="DE" term="%22Clock+distribution+networks%22">Clock distribution networks</searchLink><br /><searchLink fieldCode="DE" term="%22Integrated+circuits%22">Integrated circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Complementary+metal+oxide+semiconductors%22">Complementary metal oxide semiconductors</searchLink><br /><searchLink fieldCode="DE" term="%22Energy+dissipation%22">Energy dissipation</searchLink><br /><searchLink fieldCode="DE" term="%22Buffer+storage+%28Computer+science%29%22">Buffer storage (Computer science)</searchLink><br /><searchLink fieldCode="DE" term="%22Through-silicon+via%22">Through-silicon via</searchLink><br /><searchLink fieldCode="DE" term="%22Algorithms%22">Algorithms</searchLink>
– Name: Abstract
  Label: Abstract
  Group: Ab
  Data: Three-Dimensional (3D) Integrated Circuits (ICs) offers integrating capabilities of 'More than Moore' while overcoming CMOS scaling limitations, providing the advantages of low power, high performance and reduced costs. The design of the Clock Distribution Network (CDN) for a 3D IC has to be done meticulously to guarantee reliable operation. In the design of the CDN, clock buffers are crucial units that affect the clock skew, slew and power dissipated by the clock tree. In this paper, we propose a two-stage buffering technique that inserts clock buffers for slew control and skew minimization. Such a buffering technique decreases the number of buffers and power dissipated in the clock tree when compared to previous works which were inserting buffers primarily for slew control. We incorporate the proposed buffering technique into the 3D clock tree synthesis algorithm of previous work and evaluate the performance of the clock tree for both single Through-Silicon Vias (TSV) and mutiple TSV approach. When evaluated on IBM benchmarks (r1-r5), our buffering technique results in 25-28% reduction in buffer count and 25-29% reduction in power for single TSV-based 3D CDN. For multi-TSV approach, the performance of our work is even better:around 31-38% reduction in buffer count and 32-39% reduction in power. [ABSTRACT FROM AUTHOR]
– Name: AbstractSuppliedCopyright
  Label:
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  Data: <i>Copyright of Journal of Circuits, Systems & Computers is the property of World Scientific Publishing Company and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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        Value: 10.1142/S0218126616501425
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      – Code: eng
        Text: English
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        PageCount: 17
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    Subjects:
      – SubjectFull: Clock distribution networks
        Type: general
      – SubjectFull: Integrated circuits
        Type: general
      – SubjectFull: Complementary metal oxide semiconductors
        Type: general
      – SubjectFull: Energy dissipation
        Type: general
      – SubjectFull: Buffer storage (Computer science)
        Type: general
      – SubjectFull: Through-silicon via
        Type: general
      – SubjectFull: Algorithms
        Type: general
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      – TitleFull: Minimal Buffer Insertion Based Low Power Clock Tree Synthesis for 3D Integrated Circuits.
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            NameFull: Sumanth Kumar, Kamineni
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            NameFull: Reuben, John
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            – D: 01
              M: 11
              Text: Nov2016
              Type: published
              Y: 2016
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