View in EDS

A High-Swing 45 Gb/s Hybrid Voltage and Current-Mode PAM-4 Transmitter in 28 nm CMOS FDSOI.

Saved in:

Bibliographic Details
Title:	A High-Swing 45 Gb/s Hybrid Voltage and Current-Mode PAM-4 Transmitter in 28 nm CMOS FDSOI.
Authors:	Bassi, Matteo¹, Radice, Francesco², Bruccoleri, Melchiorre², Erba, Simone³, Mazzanti, Andrea¹
Source:	IEEE Journal of Solid-State Circuits. Nov2016, Vol. 51 Issue 11, p2702-2715. 14p.
Subjects:	Transmitters (Communication), Complementary metal oxide semiconductors, Decision feedback equalizers, Equalizers (Electronics), Circuit feedback
Abstract:	Pushed by the ever-increasing demand of high-speed connectivity, next generation 400 Gb/s electrical links are targeting PAM-4 modulation to limit channel loss and preserve link budget. Compared to NRZ, a higher amplitude is desirable to counteract the 1/3 reduction of PAM-4 vertical eye opening. However, linearity is also key, and PAM-4 levels must be precisely spaced to preserve the horizontal eye opening advantage it has over NRZ. This paper presents a 45 Gb/s PAM-4 transmitter able to deliver a very large output swing with enhanced linearity and state-of-the-art efficiency. Built around a hybrid combination of current-mode and voltage-mode topologies, the driver is embedded into a 4-taps 5-bits feed-forward equalizer (FFE), and allows tuning the output impedance to ensure good source termination. Implemented in 28 nm CMOS FDSOI process, the full transmitter includes a half-rate serializer, duty-cycle correction circuit, $>>2$ kV HBM ESD diodes, and delivers a full swing of 1.3 Vppd at 45 Gb/s, while drawing only 120 mA from 1 V supply. The power efficiency is $\sim ~2$ times better than previously reported PAM-4 transmitters. [ABSTRACT FROM PUBLISHER]
	Copyright of IEEE Journal of Solid-State Circuits is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
Database:	Engineering Source

Description
Abstract:	Pushed by the ever-increasing demand of high-speed connectivity, next generation 400 Gb/s electrical links are targeting PAM-4 modulation to limit channel loss and preserve link budget. Compared to NRZ, a higher amplitude is desirable to counteract the 1/3 reduction of PAM-4 vertical eye opening. However, linearity is also key, and PAM-4 levels must be precisely spaced to preserve the horizontal eye opening advantage it has over NRZ. This paper presents a 45 Gb/s PAM-4 transmitter able to deliver a very large output swing with enhanced linearity and state-of-the-art efficiency. Built around a hybrid combination of current-mode and voltage-mode topologies, the driver is embedded into a 4-taps 5-bits feed-forward equalizer (FFE), and allows tuning the output impedance to ensure good source termination. Implemented in 28 nm CMOS FDSOI process, the full transmitter includes a half-rate serializer, duty-cycle correction circuit, $>>2$ kV HBM ESD diodes, and delivers a full swing of 1.3 Vppd at 45 Gb/s, while drawing only 120 mA from 1 V supply. The power efficiency is $\sim ~2$ times better than previously reported PAM-4 transmitters. [ABSTRACT FROM PUBLISHER]
ISSN:	00189200
DOI:	10.1109/JSSC.2016.2598223