A Low Power 32 Bit CMOS ROM Using a Novel ATD Circuit.

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Bibliographic Details
Title:	A Low Power 32 Bit CMOS ROM Using a Novel ATD Circuit.
Authors:	Kukrety, Sidhant¹ siddhantkukreti@gmail.com, Singh, Gurmohan¹, Sulochana, Vemu¹
Source:	International Journal of Electrical & Computer Engineering (2088-8708). Aug2013, Vol. 3 Issue 4, p509-515. 7p.
Subjects:	Read-only memory, CMOS memory circuits, Electric potential, Decoders (Electronics), Signal processing, Low voltage systems, Comparative studies
Abstract:	A low power high speed 32 Bit ROM circuit implemented on 0.18µm CMOS process has been presented in this paper. The circuit is build using a parallel ROM core structure and runs on 1.8 V supply voltage. A novel Address Transition Decoder (ATD) circuit is proposed which energizes the ROM components such as Row Decoder, Column Decoder, ROM core etc, for short time intervals when there is a transition in input address bits. The power consumed in ROM with proposed ATD circuit is 0.78 mW, which corresponds to 82.27% reduction in power as compared to ROM without ATD circuit (4.46 mW). At the output almost full signal swing has been achieved without using any sense amplifier. The implemented ROM has a very low latency of 0.56 ns. [ABSTRACT FROM AUTHOR]
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Database:	Engineering Source

Description
Abstract:	A low power high speed 32 Bit ROM circuit implemented on 0.18µm CMOS process has been presented in this paper. The circuit is build using a parallel ROM core structure and runs on 1.8 V supply voltage. A novel Address Transition Decoder (ATD) circuit is proposed which energizes the ROM components such as Row Decoder, Column Decoder, ROM core etc, for short time intervals when there is a transition in input address bits. The power consumed in ROM with proposed ATD circuit is 0.78 mW, which corresponds to 82.27% reduction in power as compared to ROM without ATD circuit (4.46 mW). At the output almost full signal swing has been achieved without using any sense amplifier. The implemented ROM has a very low latency of 0.56 ns. [ABSTRACT FROM AUTHOR]
ISSN:	20888708