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Two-dimensional distributed amplifier by 2D-LC lattice.

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Bibliographic Details
Title: Two-dimensional distributed amplifier by 2D-LC lattice.
Authors: Mogheyse, Amir Hamze1 a.h.mogheyseh@stu.nit.ac.ir, Miar Naimi, Hossein1
Source: IET Microwaves, Antennas & Propagation (Wiley-Blackwell). 2016, Vol. 10 Issue 14, p1581-1590. 10p.
Subjects: Electric lines, Distributed amplifiers, Electromagnetic devices, Simulation methods & models, Distributed parameter networks
Abstract: In this study a new configuration for distributed amplifiers (DAs) is presented for the first time. Using two-dimensional (2D) LC lattices instead of one-dimensional transmission lines leads to 2D wave propagation. This configuration can cover the traditional problem of increasing conventional DA stages by decreasing the distance of power sources to the load. This new additive gain mechanism uses an electrical funnel to add the drain powers. Gain and noise relations are extracted and a broad band, high gain, low noise DA with reasonable DC power consumption is designed. Circuit layout is presented and all inductors and connections are simulated by advanced design system electromagnetic simulator with TSMC 0.18 CMOS layout specifications. Good agreements between post layout simulation results and the presented relations are achieved. The final design shows a 21.8 dB gain along 0.7 to 43.9 GHz band width. The circuit consumes only 183 mw DC power and it shows noise figure less than 7.8 dB. The output power of this circuit at 1-dB output compression point (OP1dB) is more than 8.1 dBm. The proposed technique yields excellent performance in comparison with other design techniques. [ABSTRACT FROM AUTHOR]
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Database: Engineering Source
Description
Abstract:In this study a new configuration for distributed amplifiers (DAs) is presented for the first time. Using two-dimensional (2D) LC lattices instead of one-dimensional transmission lines leads to 2D wave propagation. This configuration can cover the traditional problem of increasing conventional DA stages by decreasing the distance of power sources to the load. This new additive gain mechanism uses an electrical funnel to add the drain powers. Gain and noise relations are extracted and a broad band, high gain, low noise DA with reasonable DC power consumption is designed. Circuit layout is presented and all inductors and connections are simulated by advanced design system electromagnetic simulator with TSMC 0.18 CMOS layout specifications. Good agreements between post layout simulation results and the presented relations are achieved. The final design shows a 21.8 dB gain along 0.7 to 43.9 GHz band width. The circuit consumes only 183 mw DC power and it shows noise figure less than 7.8 dB. The output power of this circuit at 1-dB output compression point (OP1dB) is more than 8.1 dBm. The proposed technique yields excellent performance in comparison with other design techniques. [ABSTRACT FROM AUTHOR]
ISSN:17518725
DOI:10.1049/iet-map.2016.0551