Design and Simulation of 6T SRAM Cell Architectures in 32nm Technology.
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| Title: | Design and Simulation of 6T SRAM Cell Architectures in 32nm Technology. |
|---|---|
| Authors: | Apostolidis, G.1, Balobas, D.1, Konofaos, N.1 nkonofao@csd.auth.gr |
| Source: | Journal of Engineering Science & Technology Review. 2016, Vol. 9 Issue 5, p145-149. 5p. |
| Subjects: | Static random access memory chips, Computer architecture, Computer simulation, Comparative studies, Energy dissipation, Energy consumption |
| Abstract: | A comparative study of various 6T SRAM cell layouts is presented at 32 nm, including four symmetric topologies. The comparison comprises two conventional cells, a thin cell, which is the current industry standard, and a recently proposed ultrathin cell. The evaluation is based on area efficiency, power dissipation and read/write delay, all of which are calculated with proper BSIM4 level simulations. The thin-cell appears to be the best topology in both power/delay performance and area. [ABSTRACT FROM AUTHOR] |
| Copyright of Journal of Engineering Science & Technology Review is the property of Technological Education Institute of Kavala and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
| FullText | Links: – Type: pdflink Text: Availability: 0 |
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| Header | DbId: egs DbLabel: Engineering Source An: 120260030 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: Design and Simulation of 6T SRAM Cell Architectures in 32nm Technology. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Apostolidis%2C+G%2E%22">Apostolidis, G.</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Balobas%2C+D%2E%22">Balobas, D.</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Konofaos%2C+N%2E%22">Konofaos, N.</searchLink><relatesTo>1</relatesTo><i> nkonofao@csd.auth.gr</i> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22Journal+of+Engineering+Science+%26+Technology+Review%22">Journal of Engineering Science & Technology Review</searchLink>. 2016, Vol. 9 Issue 5, p145-149. 5p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Static+random+access+memory+chips%22">Static random access memory chips</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+architecture%22">Computer architecture</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+simulation%22">Computer simulation</searchLink><br /><searchLink fieldCode="DE" term="%22Comparative+studies%22">Comparative studies</searchLink><br /><searchLink fieldCode="DE" term="%22Energy+dissipation%22">Energy dissipation</searchLink><br /><searchLink fieldCode="DE" term="%22Energy+consumption%22">Energy consumption</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: A comparative study of various 6T SRAM cell layouts is presented at 32 nm, including four symmetric topologies. The comparison comprises two conventional cells, a thin cell, which is the current industry standard, and a recently proposed ultrathin cell. The evaluation is based on area efficiency, power dissipation and read/write delay, all of which are calculated with proper BSIM4 level simulations. The thin-cell appears to be the best topology in both power/delay performance and area. [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of Journal of Engineering Science & Technology Review is the property of Technological Education Institute of Kavala and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 5 StartPage: 145 Subjects: – SubjectFull: Static random access memory chips Type: general – SubjectFull: Computer architecture Type: general – SubjectFull: Computer simulation Type: general – SubjectFull: Comparative studies Type: general – SubjectFull: Energy dissipation Type: general – SubjectFull: Energy consumption Type: general Titles: – TitleFull: Design and Simulation of 6T SRAM Cell Architectures in 32nm Technology. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Apostolidis, G. – PersonEntity: Name: NameFull: Balobas, D. – PersonEntity: Name: NameFull: Konofaos, N. IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 09 Text: 2016 Type: published Y: 2016 Identifiers: – Type: issn-print Value: 17912377 Numbering: – Type: volume Value: 9 – Type: issue Value: 5 Titles: – TitleFull: Journal of Engineering Science & Technology Review Type: main |
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