Bibliographic Details
| Title: |
Improved 64-bit Radix-16 Booth Multiplier Based on Partial Product Array Height Reduction. |
| Authors: |
Antelo, Elisardo1, Montuschi, Paolo2, Nannarelli, Alberto3 |
| Source: |
IEEE Transactions on Circuits & Systems. Part I: Regular Papers. Feb2017, Vol. 64 Issue 2, p409-418. 10p. |
| Subjects: |
Analog multipliers, Multiplying circuits |
| Abstract: |
In this paper, we describe an optimization for binary radix-16 (modified) Booth recoded multipliers to reduce the maximum height of the partial product columns to \lceil n/4\rceil for n=\text{64-bit} unsigned operands. This is in contrast to the conventional maximum height of \lceil(n+1)/4\rceil$. Therefore, a reduction of one unit in the maximum height is achieved. This reduction may add flexibility during the design of the pipelined multiplier to meet the design goals, it may allow further optimizations of the partial product array reduction stage in terms of area/delay/power and/or may allow additional addends to be included in the partial product array without increasing the delay. The method can be extended to Booth recoded radix-8 multipliers, signed multipliers, combined signed/unsigned multipliers, and other values of $n$. [ABSTRACT FROM PUBLISHER] |
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| Database: |
Engineering Source |
