Improved 64-bit Radix-16 Booth Multiplier Based on Partial Product Array Height Reduction.
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| Title: | Improved 64-bit Radix-16 Booth Multiplier Based on Partial Product Array Height Reduction. |
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| Authors: | Antelo, Elisardo1, Montuschi, Paolo2, Nannarelli, Alberto3 |
| Source: | IEEE Transactions on Circuits & Systems. Part I: Regular Papers. Feb2017, Vol. 64 Issue 2, p409-418. 10p. |
| Subjects: | Analog multipliers, Multiplying circuits |
| Abstract: | In this paper, we describe an optimization for binary radix-16 (modified) Booth recoded multipliers to reduce the maximum height of the partial product columns to \lceil n/4\rceil for n=\text{64-bit} unsigned operands. This is in contrast to the conventional maximum height of \lceil(n+1)/4\rceil$. Therefore, a reduction of one unit in the maximum height is achieved. This reduction may add flexibility during the design of the pipelined multiplier to meet the design goals, it may allow further optimizations of the partial product array reduction stage in terms of area/delay/power and/or may allow additional addends to be included in the partial product array without increasing the delay. The method can be extended to Booth recoded radix-8 multipliers, signed multipliers, combined signed/unsigned multipliers, and other values of $n$. [ABSTRACT FROM PUBLISHER] |
| Copyright of IEEE Transactions on Circuits & Systems. Part I: Regular Papers is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
| FullText | Text: Availability: 0 |
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| Header | DbId: egs DbLabel: Engineering Source An: 121057049 AccessLevel: 6 PubType: Periodical PubTypeId: serialPeriodical PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: Improved 64-bit Radix-16 Booth Multiplier Based on Partial Product Array Height Reduction. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Antelo%2C+Elisardo%22">Antelo, Elisardo</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Montuschi%2C+Paolo%22">Montuschi, Paolo</searchLink><relatesTo>2</relatesTo><br /><searchLink fieldCode="AR" term="%22Nannarelli%2C+Alberto%22">Nannarelli, Alberto</searchLink><relatesTo>3</relatesTo> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22IEEE+Transactions+on+Circuits+%26+Systems%2E+Part+I%3A+Regular+Papers%22">IEEE Transactions on Circuits & Systems. Part I: Regular Papers</searchLink>. Feb2017, Vol. 64 Issue 2, p409-418. 10p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Analog+multipliers%22">Analog multipliers</searchLink><br /><searchLink fieldCode="DE" term="%22Multiplying+circuits%22">Multiplying circuits</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: In this paper, we describe an optimization for binary radix-16 (modified) Booth recoded multipliers to reduce the maximum height of the partial product columns to \lceil n/4\rceil for n=\text{64-bit} unsigned operands. This is in contrast to the conventional maximum height of \lceil(n+1)/4\rceil$. Therefore, a reduction of one unit in the maximum height is achieved. This reduction may add flexibility during the design of the pipelined multiplier to meet the design goals, it may allow further optimizations of the partial product array reduction stage in terms of area/delay/power and/or may allow additional addends to be included in the partial product array without increasing the delay. The method can be extended to Booth recoded radix-8 multipliers, signed multipliers, combined signed/unsigned multipliers, and other values of $n$. [ABSTRACT FROM PUBLISHER] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of IEEE Transactions on Circuits & Systems. Part I: Regular Papers is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1109/TCSI.2016.2561518 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 10 StartPage: 409 Subjects: – SubjectFull: Analog multipliers Type: general – SubjectFull: Multiplying circuits Type: general Titles: – TitleFull: Improved 64-bit Radix-16 Booth Multiplier Based on Partial Product Array Height Reduction. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Antelo, Elisardo – PersonEntity: Name: NameFull: Montuschi, Paolo – PersonEntity: Name: NameFull: Nannarelli, Alberto IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 02 Text: Feb2017 Type: published Y: 2017 Identifiers: – Type: issn-print Value: 15498328 Numbering: – Type: volume Value: 64 – Type: issue Value: 2 Titles: – TitleFull: IEEE Transactions on Circuits & Systems. Part I: Regular Papers Type: main |
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