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A 16 b Multi-Step Incremental Analog-to-Digital Converter With Single-Opamp Multi-Slope Extended Counting.

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Title: A 16 b Multi-Step Incremental Analog-to-Digital Converter With Single-Opamp Multi-Slope Extended Counting.
Authors: Zhang, Yi1, Chen, Chia-Hung2, He, Tao2, Temes, Gabor C.2
Source: IEEE Journal of Solid-State Circuits. Apr2017, Vol. 52 Issue 4, p1066-1076. 11p.
Subjects: Analog-to-digital converters, Digital counters, Finite impulse response filters, Feedforward neural networks, Signal quantization
Abstract: This paper presents a multi-step incremental analog-to-digital converter (IADC) using multi-slope extended counting. Only one active integrator is used in the three-step conversion cycle. The accuracy of the IADC is extended by having it configured asmulti-slope ADCs in two additional steps. The proposed IADC uses the same circuitry as a first-order IADC (IADC1), but it exhibits better performance than a second-order IADC. For the same accuracy, the conversion cycle is shortened by a large factor (by more than 29 for the implemented device) compared with that of a conventional single-step IADC1. Fabricated in 0.18 \mu \textm CMOS process, the prototype ADC occupies 0.5 mm2. With a 642 kHz clock, it achieves an SNDR of 52.2 dB in the first step. The SNDR is boosted to 79.8 dB in the second step and to 96.8 dB in the third step, over a 1 kHz signal band. The power consumption is 35 \mu \textW from a 1.5 V power supply. This gives an excellent Schreier figure of merit of 174.6 dB. [ABSTRACT FROM AUTHOR]
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Abstract:This paper presents a multi-step incremental analog-to-digital converter (IADC) using multi-slope extended counting. Only one active integrator is used in the three-step conversion cycle. The accuracy of the IADC is extended by having it configured asmulti-slope ADCs in two additional steps. The proposed IADC uses the same circuitry as a first-order IADC (IADC1), but it exhibits better performance than a second-order IADC. For the same accuracy, the conversion cycle is shortened by a large factor (by more than 29 for the implemented device) compared with that of a conventional single-step IADC1. Fabricated in 0.18 \mu \textm CMOS process, the prototype ADC occupies 0.5 mm2. With a 642 kHz clock, it achieves an SNDR of 52.2 dB in the first step. The SNDR is boosted to 79.8 dB in the second step and to 96.8 dB in the third step, over a 1 kHz signal band. The power consumption is 35 \mu \textW from a 1.5 V power supply. This gives an excellent Schreier figure of merit of 174.6 dB. [ABSTRACT FROM AUTHOR]
ISSN:00189200
DOI:10.1109/JSSC.2016.2641466