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Thermal Aware SOC Testing by Introducing Cooling Period.

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Title: Thermal Aware SOC Testing by Introducing Cooling Period.
Authors: Sarkar, Trupa1, Chakraborty, Shrabanti1, Paul, Bikram1, Pradhan, Sambhu Nath1
Source: IETE Technical Review. Mar2017, Vol. 34 Issue 2, p113-121. 9p.
Subjects: Systems on a chip testing, Cooling, Thermal comfort, Genetic algorithms, Temperature measurements
Abstract: Power and temperature constraint system-on-chip (SOC) testing is currently a major research topic. Because of increasing technology scaling and increase in device density of SOC, overheating is becoming a serious problem in the case of SOC testing. Most of the conventional power constrained test scheduling algorithms are unable to meet the temperature constraint. In this paper, two approaches of reducing test power and temperature of individual circuit and SOC have been presented. First approach considers reduction of leakage (which depends on previous pattern) during testing by ordering the test patterns. In the second approach, temperature aware SOC testing is considered. The cores of the SOC are tested with the ordered test patterns in a tactful way by introducing cooling time such that overall temperature of the SOC is reduced. Genetic algorithm (GA) based approach is used to minimize the total power and the temperature during testing by introducing cooling time between consecutive test patterns which are generated using ATALANTA for stuck-at fault model. Using this proposed technique, average saving of temperature is up to 91% when sufficient cooling period is introduced between consecutive test patterns. [ABSTRACT FROM AUTHOR]
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Database: Engineering Source
Description
Abstract:Power and temperature constraint system-on-chip (SOC) testing is currently a major research topic. Because of increasing technology scaling and increase in device density of SOC, overheating is becoming a serious problem in the case of SOC testing. Most of the conventional power constrained test scheduling algorithms are unable to meet the temperature constraint. In this paper, two approaches of reducing test power and temperature of individual circuit and SOC have been presented. First approach considers reduction of leakage (which depends on previous pattern) during testing by ordering the test patterns. In the second approach, temperature aware SOC testing is considered. The cores of the SOC are tested with the ordered test patterns in a tactful way by introducing cooling time such that overall temperature of the SOC is reduced. Genetic algorithm (GA) based approach is used to minimize the total power and the temperature during testing by introducing cooling time between consecutive test patterns which are generated using ATALANTA for stuck-at fault model. Using this proposed technique, average saving of temperature is up to 91% when sufficient cooling period is introduced between consecutive test patterns. [ABSTRACT FROM AUTHOR]
ISSN:02564602
DOI:10.1080/02564602.2016.1152914