Thermal Aware SOC Testing by Introducing Cooling Period.
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| Title: | Thermal Aware SOC Testing by Introducing Cooling Period. |
|---|---|
| Authors: | Sarkar, Trupa1, Chakraborty, Shrabanti1, Paul, Bikram1, Pradhan, Sambhu Nath1 |
| Source: | IETE Technical Review. Mar2017, Vol. 34 Issue 2, p113-121. 9p. |
| Subjects: | Systems on a chip testing, Cooling, Thermal comfort, Genetic algorithms, Temperature measurements |
| Abstract: | Power and temperature constraint system-on-chip (SOC) testing is currently a major research topic. Because of increasing technology scaling and increase in device density of SOC, overheating is becoming a serious problem in the case of SOC testing. Most of the conventional power constrained test scheduling algorithms are unable to meet the temperature constraint. In this paper, two approaches of reducing test power and temperature of individual circuit and SOC have been presented. First approach considers reduction of leakage (which depends on previous pattern) during testing by ordering the test patterns. In the second approach, temperature aware SOC testing is considered. The cores of the SOC are tested with the ordered test patterns in a tactful way by introducing cooling time such that overall temperature of the SOC is reduced. Genetic algorithm (GA) based approach is used to minimize the total power and the temperature during testing by introducing cooling time between consecutive test patterns which are generated using ATALANTA for stuck-at fault model. Using this proposed technique, average saving of temperature is up to 91% when sufficient cooling period is introduced between consecutive test patterns. [ABSTRACT FROM AUTHOR] |
| Copyright of IETE Technical Review is the property of Taylor & Francis Ltd and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
| FullText | Text: Availability: 0 |
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| Header | DbId: egs DbLabel: Engineering Source An: 122728407 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: Thermal Aware SOC Testing by Introducing Cooling Period. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Sarkar%2C+Trupa%22">Sarkar, Trupa</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Chakraborty%2C+Shrabanti%22">Chakraborty, Shrabanti</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Paul%2C+Bikram%22">Paul, Bikram</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Pradhan%2C+Sambhu+Nath%22">Pradhan, Sambhu Nath</searchLink><relatesTo>1</relatesTo> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22IETE+Technical+Review%22">IETE Technical Review</searchLink>. Mar2017, Vol. 34 Issue 2, p113-121. 9p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Systems+on+a+chip+testing%22">Systems on a chip testing</searchLink><br /><searchLink fieldCode="DE" term="%22Cooling%22">Cooling</searchLink><br /><searchLink fieldCode="DE" term="%22Thermal+comfort%22">Thermal comfort</searchLink><br /><searchLink fieldCode="DE" term="%22Genetic+algorithms%22">Genetic algorithms</searchLink><br /><searchLink fieldCode="DE" term="%22Temperature+measurements%22">Temperature measurements</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: Power and temperature constraint system-on-chip (SOC) testing is currently a major research topic. Because of increasing technology scaling and increase in device density of SOC, overheating is becoming a serious problem in the case of SOC testing. Most of the conventional power constrained test scheduling algorithms are unable to meet the temperature constraint. In this paper, two approaches of reducing test power and temperature of individual circuit and SOC have been presented. First approach considers reduction of leakage (which depends on previous pattern) during testing by ordering the test patterns. In the second approach, temperature aware SOC testing is considered. The cores of the SOC are tested with the ordered test patterns in a tactful way by introducing cooling time such that overall temperature of the SOC is reduced. Genetic algorithm (GA) based approach is used to minimize the total power and the temperature during testing by introducing cooling time between consecutive test patterns which are generated using ATALANTA for stuck-at fault model. Using this proposed technique, average saving of temperature is up to 91% when sufficient cooling period is introduced between consecutive test patterns. [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of IETE Technical Review is the property of Taylor & Francis Ltd and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1080/02564602.2016.1152914 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 9 StartPage: 113 Subjects: – SubjectFull: Systems on a chip testing Type: general – SubjectFull: Cooling Type: general – SubjectFull: Thermal comfort Type: general – SubjectFull: Genetic algorithms Type: general – SubjectFull: Temperature measurements Type: general Titles: – TitleFull: Thermal Aware SOC Testing by Introducing Cooling Period. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Sarkar, Trupa – PersonEntity: Name: NameFull: Chakraborty, Shrabanti – PersonEntity: Name: NameFull: Paul, Bikram – PersonEntity: Name: NameFull: Pradhan, Sambhu Nath IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 03 Text: Mar2017 Type: published Y: 2017 Identifiers: – Type: issn-print Value: 02564602 Numbering: – Type: volume Value: 34 – Type: issue Value: 2 Titles: – TitleFull: IETE Technical Review Type: main |
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