Bibliographic Details
| Title: |
Energy-Aware Modeling of Scaled Heterogeneous Systems. |
| Authors: |
Marowka, Ami1 amimar2@yahoo.com |
| Source: |
International Journal of Parallel Programming. Oct2017, Vol. 45 Issue 5, p1026-1045. 20p. |
| Subjects: |
Energy consumption management, Microprocessor energy consumption, Microprocessor design & construction, Chip scale packaging, Moore's law |
| Abstract: |
Many-core processors are accelerating the performance of contemporary high-performance systems. Managing power consumption within these systems demands low-power architectures to increase power savings. One of the promising solutions offered today by microprocessor architects is asymmetric microprocessors that integrate different core architectures on a single die. This paper presents analytical models based on scaled power metrics to analyze the impact of various architectural design choices on scaled performance and power savings. The power consumption implications of different processing schemes and various chip configurations were also analyzed. Analysis shows that by choosing the optimal chip configuration, energy efficiency and energy savings can be increased considerably. [ABSTRACT FROM AUTHOR] |
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| Database: |
Engineering Source |
