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Fully digital fast transient phase-locked digital LDO-embedded-MDLL for DVFS applications.

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Title: Fully digital fast transient phase-locked digital LDO-embedded-MDLL for DVFS applications.
Authors: Akram, Muhammad1 abrar@kangwon.ac.kr, Hwang, In-Chul1 ihwang@kangwon.ac.kr
Source: Analog Integrated Circuits & Signal Processing. Oct2017, Vol. 93 Issue 1, p123-136. 14p.
Subjects: Multiplying circuits, Energy management, Systems on a chip, Voltage-controlled oscillators, Phase-locked loops
Abstract: This paper presents a multiplying delay-locked loop (MDLL) embedded with a frequency-only reference (F) based fully digital low-dropout regulator (DLDO) that outperforms conventional dynamic voltage and frequency scaling circuits when driving digital-load circuits that operate down to the near-threshold voltage level . We also propose a feed-forward acceleration (FFA) technique, which is dynamically activated only during the transient period to reduce the transient response time and voltage droop caused by the load current step. The proposed DLDO-embedded-MDLL was fabricated in a 40 nm CMOS process and occupies an active area of 0.02 mm. At the typical V = 1.2 V and F = 37.4 MHz, the regulated range of voltage was measured to be 0.56-1.16 V while the frequency being scaled from 0.411 to 2.35 GHz. With the proposed FFA technique, the load transient response and voltage droop were reduced by 61.5 and 35%, respectively, compared to the values during normal loop operation. In addition, the measured phase noise at 0.411 and 2.35 GHz was less than −116 and −104 dBc/Hz, respectively, both at 1 MHz offset. [ABSTRACT FROM AUTHOR]
Copyright of Analog Integrated Circuits & Signal Processing is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
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DbLabel: Engineering Source
An: 125085715
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  Data: Fully digital fast transient phase-locked digital LDO-embedded-MDLL for DVFS applications.
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  Data: <searchLink fieldCode="JN" term="%22Analog+Integrated+Circuits+%26+Signal+Processing%22">Analog Integrated Circuits & Signal Processing</searchLink>. Oct2017, Vol. 93 Issue 1, p123-136. 14p.
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  Data: <searchLink fieldCode="DE" term="%22Multiplying+circuits%22">Multiplying circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Energy+management%22">Energy management</searchLink><br /><searchLink fieldCode="DE" term="%22Systems+on+a+chip%22">Systems on a chip</searchLink><br /><searchLink fieldCode="DE" term="%22Voltage-controlled+oscillators%22">Voltage-controlled oscillators</searchLink><br /><searchLink fieldCode="DE" term="%22Phase-locked+loops%22">Phase-locked loops</searchLink>
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  Data: This paper presents a multiplying delay-locked loop (MDLL) embedded with a frequency-only reference (F) based fully digital low-dropout regulator (DLDO) that outperforms conventional dynamic voltage and frequency scaling circuits when driving digital-load circuits that operate down to the near-threshold voltage level . We also propose a feed-forward acceleration (FFA) technique, which is dynamically activated only during the transient period to reduce the transient response time and voltage droop caused by the load current step. The proposed DLDO-embedded-MDLL was fabricated in a 40 nm CMOS process and occupies an active area of 0.02 mm. At the typical V = 1.2 V and F = 37.4 MHz, the regulated range of voltage was measured to be 0.56-1.16 V while the frequency being scaled from 0.411 to 2.35 GHz. With the proposed FFA technique, the load transient response and voltage droop were reduced by 61.5 and 35%, respectively, compared to the values during normal loop operation. In addition, the measured phase noise at 0.411 and 2.35 GHz was less than −116 and −104 dBc/Hz, respectively, both at 1 MHz offset. [ABSTRACT FROM AUTHOR]
– Name: AbstractSuppliedCopyright
  Label:
  Group: Ab
  Data: <i>Copyright of Analog Integrated Circuits & Signal Processing is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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        Value: 10.1007/s10470-017-1028-x
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      – Code: eng
        Text: English
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        PageCount: 14
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        Type: general
      – SubjectFull: Energy management
        Type: general
      – SubjectFull: Systems on a chip
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      – SubjectFull: Voltage-controlled oscillators
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              Text: Oct2017
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