Bibliographic Details
| Title: |
Design of Reliable SoCs With BIST Hardware and Machine Learning. |
| Authors: |
Sadi, Mehdi1, Contreras, Gustavo K.1, Chen, Jifeng2, Winemberg, LeRoy2, Tehranipoor, Mark1 |
| Source: |
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. Nov2017, Vol. 25 Issue 11, p3237-3250. 14p. |
| Subjects: |
Machine learning, Systems on a chip, Flip-flop circuits |
| Abstract: |
In this paper, a novel framework is presented for designing lifetime-reliable SoCs with self-adaptation capability against aging-induced degradation. The proposed flow utilizes the existing logic built-in-self-test (LBIST) hardware, and software implemented machine learning predictor to activate appropriate countermeasures to remedy the wear out in the field. Using an innovative method, we convert ATPG-generated transition delay test patterns into LBIST patterns to activate high-usage critical/near-critical paths in-field, and the corresponding responses are utilized in developing the predictor. A gate-overlap and path-delay-aware algorithm selects the optimum set of patterns. The area and test time overhead for the framework are very low. We implemented our proposed flow on SoC benchmark designs, and the results demonstrated its efficacy. [ABSTRACT FROM AUTHOR] |
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| Database: |
Engineering Source |
