APA (7th ed.) Citation

Sadi, M., Contreras, G. K., Chen, J., Winemberg, L., & Tehranipoor, M. (2017). Design of Reliable SoCs With BIST Hardware and Machine Learning. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 25(11), 3237. https://doi.org/10.1109/TVLSI.2017.2734685

Chicago Style (17th ed.) Citation

Sadi, Mehdi, Gustavo K. Contreras, Jifeng Chen, LeRoy Winemberg, and Mark Tehranipoor. "Design of Reliable SoCs With BIST Hardware and Machine Learning." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25, no. 11 (2017): 3237. https://doi.org/10.1109/TVLSI.2017.2734685.

MLA (9th ed.) Citation

Sadi, Mehdi, et al. "Design of Reliable SoCs With BIST Hardware and Machine Learning." IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 11, 2017, p. 3237, https://doi.org/10.1109/TVLSI.2017.2734685.