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Investigation of BTI characteristics and its behavior on 10 nm SRAM with high-k/metal gate FinFET technology having multi-VT gate stack.

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Bibliographic Details
Title: Investigation of BTI characteristics and its behavior on 10 nm SRAM with high-k/metal gate FinFET technology having multi-VT gate stack.
Authors: Jin, Minjung1 minjung.jin@samsung.com, Kim, Kangjung1, Kim, Yoohwan1, Shim, Hyewon1, Kim, Jinju1, Kim, Gunrae1, Pae, Sangwoo1
Source: Microelectronics Reliability. Feb2018, Vol. 81, p201-209. 9p.
Subjects: Static random access memory chips, Integrated memory circuits, Transistors, Gallium nitride, Cyclic loads
Abstract: Bias-Temperature Instability (BTI) is one of the key device reliability concerns for both digital and analog circuit operations. Features of work-function metal (WFM) for V T modulation in 10 nm FinFET process technology results in WFM dependent BTI characteristics. Similar levels of aging degradation to those of previous 14 nm technology were observed in both DC and AC operations. As BTI-induced V T variability is expected to increase with 3D fin dimension scaling, such variability must be accurately characterized and considered for circuit designs. This paper reports the impact of transistor- level BTI degradation on circuits by studying Ring Oscillator (RO) and SRAM. The SRAM cell stabilities in terms of SNM (Static Noise Margin) and WRM (Write Margin) were further studied through SRAM HTOL stresses by characterizing V min shift. Robust 10 nm SRAM and product level HTOL reliability up to 500 h were demonstrated. [ABSTRACT FROM AUTHOR]
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Database: Engineering Source
Description
Abstract:Bias-Temperature Instability (BTI) is one of the key device reliability concerns for both digital and analog circuit operations. Features of work-function metal (WFM) for V T modulation in 10 nm FinFET process technology results in WFM dependent BTI characteristics. Similar levels of aging degradation to those of previous 14 nm technology were observed in both DC and AC operations. As BTI-induced V T variability is expected to increase with 3D fin dimension scaling, such variability must be accurately characterized and considered for circuit designs. This paper reports the impact of transistor- level BTI degradation on circuits by studying Ring Oscillator (RO) and SRAM. The SRAM cell stabilities in terms of SNM (Static Noise Margin) and WRM (Write Margin) were further studied through SRAM HTOL stresses by characterizing V min shift. Robust 10 nm SRAM and product level HTOL reliability up to 500 h were demonstrated. [ABSTRACT FROM AUTHOR]
ISSN:00262714
DOI:10.1016/j.microrel.2017.12.014