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Analysis and Design of a 30- to 220-GHz Balanced Cascaded Single-Stage Distributed Amplifier in 130-nm SiGe BiCMOS.

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Bibliographic Details
Title: Analysis and Design of a 30- to 220-GHz Balanced Cascaded Single-Stage Distributed Amplifier in 130-nm SiGe BiCMOS.
Authors: Testa, Paolo Valerio1 paolo_valerio.testa@tu-dresden.de, Carta, Corrado1, Jorges, Udo1, Ellinger, Frank1
Source: IEEE Journal of Solid-State Circuits. May2018, Vol. 53 Issue 5, p1457-1467. 11p.
Subjects: BiCMOS logic circuits, Distributed amplifiers, Silicon germanium integrated circuits
Abstract: This paper describes a novel distributed amplifier (DA) architecture for ultra-wide band of operation at millimeter-wave frequency. The DA consists of two cascaded single-stage DAs (CSSDAs) embedded in a balanced architecture. The implemented design retains the benefits of CSSDAs in terms of high maximum frequency, broad band of operation, and compact area, while significantly improving the amplifier input and output matching and its linearity with the balanced architecture, which are the major issues of this class of circuits. The small-signal analysis is provided in detail and explains the nature of the poor output matching typical of this class of DAs. Furthermore, the CSSDA gain is calculated as function of frequency and circuit parameters, extending available literature results, and providing direct design guidelines with a compact formula. Experimental validation is demonstrated with the fabrication of a circuit prototype in a 130-nm SiGe BiCMOS process. The circuit is able to provide an average of 16-dB gain over the frequency band 30–220 GHz, with input- and output-return losses above 10 dB, and a maximum measured output-referred 1-dB compression point of 4.5 dBm. To the best knowledge of the authors, the measured matching and linearity are the best reported for CSSDAs. [ABSTRACT FROM AUTHOR]
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Database: Engineering Source
Description
Abstract:This paper describes a novel distributed amplifier (DA) architecture for ultra-wide band of operation at millimeter-wave frequency. The DA consists of two cascaded single-stage DAs (CSSDAs) embedded in a balanced architecture. The implemented design retains the benefits of CSSDAs in terms of high maximum frequency, broad band of operation, and compact area, while significantly improving the amplifier input and output matching and its linearity with the balanced architecture, which are the major issues of this class of circuits. The small-signal analysis is provided in detail and explains the nature of the poor output matching typical of this class of DAs. Furthermore, the CSSDA gain is calculated as function of frequency and circuit parameters, extending available literature results, and providing direct design guidelines with a compact formula. Experimental validation is demonstrated with the fabrication of a circuit prototype in a 130-nm SiGe BiCMOS process. The circuit is able to provide an average of 16-dB gain over the frequency band 30–220 GHz, with input- and output-return losses above 10 dB, and a maximum measured output-referred 1-dB compression point of 4.5 dBm. To the best knowledge of the authors, the measured matching and linearity are the best reported for CSSDAs. [ABSTRACT FROM AUTHOR]
ISSN:00189200
DOI:10.1109/JSSC.2018.2797240