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Analysis and Design of a 30- to 220-GHz Balanced Cascaded Single-Stage Distributed Amplifier in 130-nm SiGe BiCMOS.

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Title: Analysis and Design of a 30- to 220-GHz Balanced Cascaded Single-Stage Distributed Amplifier in 130-nm SiGe BiCMOS.
Authors: Testa, Paolo Valerio1 paolo_valerio.testa@tu-dresden.de, Carta, Corrado1, Jorges, Udo1, Ellinger, Frank1
Source: IEEE Journal of Solid-State Circuits. May2018, Vol. 53 Issue 5, p1457-1467. 11p.
Subjects: BiCMOS logic circuits, Distributed amplifiers, Silicon germanium integrated circuits
Abstract: This paper describes a novel distributed amplifier (DA) architecture for ultra-wide band of operation at millimeter-wave frequency. The DA consists of two cascaded single-stage DAs (CSSDAs) embedded in a balanced architecture. The implemented design retains the benefits of CSSDAs in terms of high maximum frequency, broad band of operation, and compact area, while significantly improving the amplifier input and output matching and its linearity with the balanced architecture, which are the major issues of this class of circuits. The small-signal analysis is provided in detail and explains the nature of the poor output matching typical of this class of DAs. Furthermore, the CSSDA gain is calculated as function of frequency and circuit parameters, extending available literature results, and providing direct design guidelines with a compact formula. Experimental validation is demonstrated with the fabrication of a circuit prototype in a 130-nm SiGe BiCMOS process. The circuit is able to provide an average of 16-dB gain over the frequency band 30–220 GHz, with input- and output-return losses above 10 dB, and a maximum measured output-referred 1-dB compression point of 4.5 dBm. To the best knowledge of the authors, the measured matching and linearity are the best reported for CSSDAs. [ABSTRACT FROM AUTHOR]
Copyright of IEEE Journal of Solid-State Circuits is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
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DbLabel: Engineering Source
An: 130091839
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  Data: Analysis and Design of a 30- to 220-GHz Balanced Cascaded Single-Stage Distributed Amplifier in 130-nm SiGe BiCMOS.
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  Data: <searchLink fieldCode="AR" term="%22Testa%2C+Paolo+Valerio%22">Testa, Paolo Valerio</searchLink><relatesTo>1</relatesTo><i> paolo_valerio.testa@tu-dresden.de</i><br /><searchLink fieldCode="AR" term="%22Carta%2C+Corrado%22">Carta, Corrado</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Jorges%2C+Udo%22">Jorges, Udo</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Ellinger%2C+Frank%22">Ellinger, Frank</searchLink><relatesTo>1</relatesTo>
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  Data: <searchLink fieldCode="JN" term="%22IEEE+Journal+of+Solid-State+Circuits%22">IEEE Journal of Solid-State Circuits</searchLink>. May2018, Vol. 53 Issue 5, p1457-1467. 11p.
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  Data: <searchLink fieldCode="DE" term="%22BiCMOS+logic+circuits%22">BiCMOS logic circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Distributed+amplifiers%22">Distributed amplifiers</searchLink><br /><searchLink fieldCode="DE" term="%22Silicon+germanium+integrated+circuits%22">Silicon germanium integrated circuits</searchLink>
– Name: Abstract
  Label: Abstract
  Group: Ab
  Data: This paper describes a novel distributed amplifier (DA) architecture for ultra-wide band of operation at millimeter-wave frequency. The DA consists of two cascaded single-stage DAs (CSSDAs) embedded in a balanced architecture. The implemented design retains the benefits of CSSDAs in terms of high maximum frequency, broad band of operation, and compact area, while significantly improving the amplifier input and output matching and its linearity with the balanced architecture, which are the major issues of this class of circuits. The small-signal analysis is provided in detail and explains the nature of the poor output matching typical of this class of DAs. Furthermore, the CSSDA gain is calculated as function of frequency and circuit parameters, extending available literature results, and providing direct design guidelines with a compact formula. Experimental validation is demonstrated with the fabrication of a circuit prototype in a 130-nm SiGe BiCMOS process. The circuit is able to provide an average of 16-dB gain over the frequency band 30–220 GHz, with input- and output-return losses above 10 dB, and a maximum measured output-referred 1-dB compression point of 4.5 dBm. To the best knowledge of the authors, the measured matching and linearity are the best reported for CSSDAs. [ABSTRACT FROM AUTHOR]
– Name: AbstractSuppliedCopyright
  Label:
  Group: Ab
  Data: <i>Copyright of IEEE Journal of Solid-State Circuits is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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RecordInfo BibRecord:
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      – Type: doi
        Value: 10.1109/JSSC.2018.2797240
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      – Code: eng
        Text: English
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      Pagination:
        PageCount: 11
        StartPage: 1457
    Subjects:
      – SubjectFull: BiCMOS logic circuits
        Type: general
      – SubjectFull: Distributed amplifiers
        Type: general
      – SubjectFull: Silicon germanium integrated circuits
        Type: general
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      – TitleFull: Analysis and Design of a 30- to 220-GHz Balanced Cascaded Single-Stage Distributed Amplifier in 130-nm SiGe BiCMOS.
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            NameFull: Carta, Corrado
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            NameFull: Jorges, Udo
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            NameFull: Ellinger, Frank
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              M: 05
              Text: May2018
              Type: published
              Y: 2018
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            – TitleFull: IEEE Journal of Solid-State Circuits
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