Bibliographic Details
| Title: |
DCMCS: Highly Robust Low-Power Differential Current-Mode Clocking and Synthesis. |
| Authors: |
Islam, Riadul, Fahmy, Hany A., Lin, Ping Y., Guthaus, Matthew R. |
| Source: |
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. Oct2018, Vol. 26 Issue 10, p2108-2117. 10p. |
| Subjects: |
Technology, Clock distribution networks, Electric potential, Methodology, Electrodiffusion |
| Abstract: |
In this paper, we present a new differential current-mode pulsed flip-flop (DCMPFF) for low-power clock distribution using a representative 45-nm CMOS technology. Experimental results show that the DCMPFF has a 47% faster clock-to-output (CLK-Q) delay than a traditional voltagemode (VM)-pulsed FF. When the DCMPFF is integrated with a DCM H-tree clock distribution, the differential technique saves 53% and 26% power compared to conventional VM and previous current-mode (CM) clock networks, respectively. In addition, we propose the first DCM clocking and synthesis (DCMCS) methodology to improve the robustness and overall clock power of a network. The proposed DCMCS-based electromigrationaware clocking saves 79% and 51% average power with 7.7 and 11.3 ps lower clock skew when the DCM scheme is applied to ISPD 2009 and 2010 test benches, respectively. [ABSTRACT FROM AUTHOR] |
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| Database: |
Engineering Source |
