Bibliographic Details
| Title: |
Slew Merging Region Propagation for Bounded Slew and Skew Clock Tree Synthesis. |
| Authors: |
Lerner, Scott, Taskin, Baris |
| Source: |
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. Jan2019, Vol. 27 Issue 1, p1-10. 10p. |
| Subjects: |
Mathematical models, Clock distribution networks |
| Abstract: |
Building clock trees for tight skew constraints of clock delivery networks is standard in the industry. Tight slew constraints of high-performance designs require post-processing techniques to satisfy slew constraints after clock tree synthesis (CTS). Post-processing adversely impacts the power dissipation. This paper proposes slew merging region CTS (SMRcts); a novel algorithm to satisfy bounded slew and skew constraints simultaneously during synthesis. Experimental results performed on International Symposium on Physical Design (ISPD) 2010 benchmarks using a 20-nm FinFET technology show an average reduction of 15% power over a bounded skew approach. Comparison to the ISPD 2010 CTS contest solutions in the literature shows SMRcts producing a 51% improvement in a utility metric. Scalability of SMRcts is demonstrated on ISPD 2013 benchmarks with up to 100k sinks. [ABSTRACT FROM AUTHOR] |
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| Database: |
Engineering Source |
