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IBM z14: Processor Characterization and Power Management for High-Reliability Mainframe Systems.

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Title: IBM z14: Processor Characterization and Power Management for High-Reliability Mainframe Systems.
Authors: Berry, Christopher, Wolpert, David, Vezrytzis, Christos, Rizzolo, Richard, Carey, Sean, Maroz, Yaniv, Shi, Hunter, Chidambarrao, Dureseti, Jacobi, Christian, Saporito, Anthony, Strach, Thomas, Buyuktosunoglu, Alper, Lobo, Preetham, Chuang, Pierce, Owczarczyk, Pawel, Bertran, Ramon, Webel, Tobias, Restle, Phillip J.
Source: IEEE Journal of Solid-State Circuits. Jan2019, Vol. 54 Issue 1, p121-132. 12p.
Subjects: Mainframe computers, IBM computers, Energy management
Abstract: The IBM z14 is the latest update in the storied history of IBM mainframes. Reliability, availability, security, and scalability are the foundation of the IBM mainframe line. System reliability and availability targets are in excess of 10 years, requiring rigorous chip characterization processes. In this paper, we discuss some of the many processes used to ensure that lifetime. An additional part of this reliability is power management (PM). The 5.2-GHz high-power design of the central processor chip requires advanced on-die PM capabilities to adapt to power intensive instruction streams. We also discuss a number of improvements to the critical path monitoring design used to manage power supply voltage droops, reducing response time and the impact on system performance. Finally, we compare a set of simulations and hardware results to validate our power fluctuation models. [ABSTRACT FROM AUTHOR]
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Database: Engineering Source
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Abstract:The IBM z14 is the latest update in the storied history of IBM mainframes. Reliability, availability, security, and scalability are the foundation of the IBM mainframe line. System reliability and availability targets are in excess of 10 years, requiring rigorous chip characterization processes. In this paper, we discuss some of the many processes used to ensure that lifetime. An additional part of this reliability is power management (PM). The 5.2-GHz high-power design of the central processor chip requires advanced on-die PM capabilities to adapt to power intensive instruction streams. We also discuss a number of improvements to the critical path monitoring design used to manage power supply voltage droops, reducing response time and the impact on system performance. Finally, we compare a set of simulations and hardware results to validate our power fluctuation models. [ABSTRACT FROM AUTHOR]
ISSN:00189200
DOI:10.1109/JSSC.2018.2873582