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Design of a 2–12-GHz Bidirectional Distributed Amplifier in a 0.18- $\mu$ m CMOS Technology.

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Title: Design of a 2–12-GHz Bidirectional Distributed Amplifier in a 0.18- $\mu$ m CMOS Technology.
Authors: Alizadeh, Amirreza, Meghdadi, Masoud, Yaghoobi, Majid, Medi, Ali
Source: IEEE Transactions on Microwave Theory & Techniques. Feb2019, Vol. 67 Issue 2, p754-764. 11p.
Subjects: Complementary metal oxide semiconductors, Distributed amplifiers, Bandwidths, Energy consumption, Integrated circuits, Electric circuits
Abstract: This paper presents the design and implementation of a bidirectional distributed amplifier (BDDA) in a 0.18- $\boldsymbol \mu \text{m}$ CMOS process. The performance of the BDDA is theoretically analyzed, and the optimum number of gain stages ($n_{\text {opt}}$), maximum achievable power gain ($G_{P}$), and circuit bandwidth are formulated. In addition, a new formula for proper choice of the number of DA stages (i.e., $n$) is offered where dc-power consumption of the circuit ($P_{\text {dc}}$) is also considered. This formula optimizes $G_{P}/P_{\text {dc}}$ , and it is preferred over the conventional $n_{\text {opt}}$ formula. To validate the theoretical analyses, a 2–12-GHz BDDA with high output 1-dB compression point of +16 dBm and small-signal gain of 10 dB is fabricated. The BDDA chip occupies 1.89-mm2 die area, and its average measured noise figure and $P_{\text {dc}}$ are 6.8 dB and 0.38 W in the high-power mode and 6.5 dB and 0.13 W in the low-power mode, respectively. [ABSTRACT FROM AUTHOR]
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Abstract:This paper presents the design and implementation of a bidirectional distributed amplifier (BDDA) in a 0.18- $\boldsymbol \mu \text{m}$ CMOS process. The performance of the BDDA is theoretically analyzed, and the optimum number of gain stages ($n_{\text {opt}}$), maximum achievable power gain ($G_{P}$), and circuit bandwidth are formulated. In addition, a new formula for proper choice of the number of DA stages (i.e., $n$) is offered where dc-power consumption of the circuit ($P_{\text {dc}}$) is also considered. This formula optimizes $G_{P}/P_{\text {dc}}$ , and it is preferred over the conventional $n_{\text {opt}}$ formula. To validate the theoretical analyses, a 2–12-GHz BDDA with high output 1-dB compression point of +16 dBm and small-signal gain of 10 dB is fabricated. The BDDA chip occupies 1.89-mm2 die area, and its average measured noise figure and $P_{\text {dc}}$ are 6.8 dB and 0.38 W in the high-power mode and 6.5 dB and 0.13 W in the low-power mode, respectively. [ABSTRACT FROM AUTHOR]
ISSN:00189480
DOI:10.1109/TMTT.2018.2883956