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Design of a 2–12-GHz Bidirectional Distributed Amplifier in a 0.18- $\mu$ m CMOS Technology.

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Title: Design of a 2–12-GHz Bidirectional Distributed Amplifier in a 0.18- $\mu$ m CMOS Technology.
Authors: Alizadeh, Amirreza, Meghdadi, Masoud, Yaghoobi, Majid, Medi, Ali
Source: IEEE Transactions on Microwave Theory & Techniques. Feb2019, Vol. 67 Issue 2, p754-764. 11p.
Subjects: Complementary metal oxide semiconductors, Distributed amplifiers, Bandwidths, Energy consumption, Integrated circuits, Electric circuits
Abstract: This paper presents the design and implementation of a bidirectional distributed amplifier (BDDA) in a 0.18- $\boldsymbol \mu \text{m}$ CMOS process. The performance of the BDDA is theoretically analyzed, and the optimum number of gain stages ($n_{\text {opt}}$), maximum achievable power gain ($G_{P}$), and circuit bandwidth are formulated. In addition, a new formula for proper choice of the number of DA stages (i.e., $n$) is offered where dc-power consumption of the circuit ($P_{\text {dc}}$) is also considered. This formula optimizes $G_{P}/P_{\text {dc}}$ , and it is preferred over the conventional $n_{\text {opt}}$ formula. To validate the theoretical analyses, a 2–12-GHz BDDA with high output 1-dB compression point of +16 dBm and small-signal gain of 10 dB is fabricated. The BDDA chip occupies 1.89-mm2 die area, and its average measured noise figure and $P_{\text {dc}}$ are 6.8 dB and 0.38 W in the high-power mode and 6.5 dB and 0.13 W in the low-power mode, respectively. [ABSTRACT FROM AUTHOR]
Copyright of IEEE Transactions on Microwave Theory & Techniques is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
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DbLabel: Engineering Source
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  Data: Design of a 2–12-GHz Bidirectional Distributed Amplifier in a 0.18- $\mu$ m CMOS Technology.
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  Data: <searchLink fieldCode="AR" term="%22Alizadeh%2C+Amirreza%22">Alizadeh, Amirreza</searchLink><br /><searchLink fieldCode="AR" term="%22Meghdadi%2C+Masoud%22">Meghdadi, Masoud</searchLink><br /><searchLink fieldCode="AR" term="%22Yaghoobi%2C+Majid%22">Yaghoobi, Majid</searchLink><br /><searchLink fieldCode="AR" term="%22Medi%2C+Ali%22">Medi, Ali</searchLink>
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  Data: <searchLink fieldCode="DE" term="%22Complementary+metal+oxide+semiconductors%22">Complementary metal oxide semiconductors</searchLink><br /><searchLink fieldCode="DE" term="%22Distributed+amplifiers%22">Distributed amplifiers</searchLink><br /><searchLink fieldCode="DE" term="%22Bandwidths%22">Bandwidths</searchLink><br /><searchLink fieldCode="DE" term="%22Energy+consumption%22">Energy consumption</searchLink><br /><searchLink fieldCode="DE" term="%22Integrated+circuits%22">Integrated circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Electric+circuits%22">Electric circuits</searchLink>
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  Label: Abstract
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  Data: This paper presents the design and implementation of a bidirectional distributed amplifier (BDDA) in a 0.18- $\boldsymbol \mu \text{m}$ CMOS process. The performance of the BDDA is theoretically analyzed, and the optimum number of gain stages ($n_{\text {opt}}$), maximum achievable power gain ($G_{P}$), and circuit bandwidth are formulated. In addition, a new formula for proper choice of the number of DA stages (i.e., $n$) is offered where dc-power consumption of the circuit ($P_{\text {dc}}$) is also considered. This formula optimizes $G_{P}/P_{\text {dc}}$ , and it is preferred over the conventional $n_{\text {opt}}$ formula. To validate the theoretical analyses, a 2–12-GHz BDDA with high output 1-dB compression point of +16 dBm and small-signal gain of 10 dB is fabricated. The BDDA chip occupies 1.89-mm2 die area, and its average measured noise figure and $P_{\text {dc}}$ are 6.8 dB and 0.38 W in the high-power mode and 6.5 dB and 0.13 W in the low-power mode, respectively. [ABSTRACT FROM AUTHOR]
– Name: AbstractSuppliedCopyright
  Label:
  Group: Ab
  Data: <i>Copyright of IEEE Transactions on Microwave Theory & Techniques is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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      – Type: doi
        Value: 10.1109/TMTT.2018.2883956
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      – Code: eng
        Text: English
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        Type: general
      – SubjectFull: Distributed amplifiers
        Type: general
      – SubjectFull: Bandwidths
        Type: general
      – SubjectFull: Energy consumption
        Type: general
      – SubjectFull: Integrated circuits
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            NameFull: Meghdadi, Masoud
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              Text: Feb2019
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