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A 130-nm Ferroelectric Nonvolatile System-on-Chip With Direct Peripheral Restore Architecture for Transient Computing System.

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Title: A 130-nm Ferroelectric Nonvolatile System-on-Chip With Direct Peripheral Restore Architecture for Transient Computing System.
Authors: Liu, Yongpan, Su, Fang, Yang, Yixiong, Wang, Zhibo, Wang, Yiqun, Li, Zewei, Li, Xueqing, Yoshimura, Ryuji, Naiki, Takashi, Tsuwa, Takashi, Saito, Takahiko, Wang, Zhongjun, Taniuchi, Koji, Yang, Huazhong
Source: IEEE Journal of Solid-State Circuits. Mar2019, Vol. 54 Issue 3, p885-895. 11p.
Subjects: Ferroelectric capacitors, Systems on a chip testing, Computer systems
Abstract: Owing to its unique capability to sustain computation progress over power outages, a nonvolatile processor (NVP) is promising for energy-harvesting-powered Internet-of-Things devices. However, the widespread application of NVP is continually blocked by the system integration issues and the configuration overheads of peripheral devices. This paper presents a nonvolatile system-on-chip (NVSoC) with improved integration level, power management flexibility, and system wake-up speed. An on-chip power management subsystem is designed to minimize the number of external components while supporting versatile power policies. And a direct peripheral restore architecture is outlined, which enables a fast and parallel re-configuration of peripheral devices after the resumption of power supply. A test chip is fabricated in a 130-nm ferroelectric-CMOS process with 22.09-mm2 area. Measurement results show 6 $\times $ higher data throughput as compared with a conventional NVP when facing power failures. [ABSTRACT FROM AUTHOR]
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Database: Engineering Source
Description
Abstract:Owing to its unique capability to sustain computation progress over power outages, a nonvolatile processor (NVP) is promising for energy-harvesting-powered Internet-of-Things devices. However, the widespread application of NVP is continually blocked by the system integration issues and the configuration overheads of peripheral devices. This paper presents a nonvolatile system-on-chip (NVSoC) with improved integration level, power management flexibility, and system wake-up speed. An on-chip power management subsystem is designed to minimize the number of external components while supporting versatile power policies. And a direct peripheral restore architecture is outlined, which enables a fast and parallel re-configuration of peripheral devices after the resumption of power supply. A test chip is fabricated in a 130-nm ferroelectric-CMOS process with 22.09-mm2 area. Measurement results show 6 $\times $ higher data throughput as compared with a conventional NVP when facing power failures. [ABSTRACT FROM AUTHOR]
ISSN:00189200
DOI:10.1109/JSSC.2018.2884349