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A 130-nm Ferroelectric Nonvolatile System-on-Chip With Direct Peripheral Restore Architecture for Transient Computing System.

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Title: A 130-nm Ferroelectric Nonvolatile System-on-Chip With Direct Peripheral Restore Architecture for Transient Computing System.
Authors: Liu, Yongpan, Su, Fang, Yang, Yixiong, Wang, Zhibo, Wang, Yiqun, Li, Zewei, Li, Xueqing, Yoshimura, Ryuji, Naiki, Takashi, Tsuwa, Takashi, Saito, Takahiko, Wang, Zhongjun, Taniuchi, Koji, Yang, Huazhong
Source: IEEE Journal of Solid-State Circuits. Mar2019, Vol. 54 Issue 3, p885-895. 11p.
Subjects: Ferroelectric capacitors, Systems on a chip testing, Computer systems
Abstract: Owing to its unique capability to sustain computation progress over power outages, a nonvolatile processor (NVP) is promising for energy-harvesting-powered Internet-of-Things devices. However, the widespread application of NVP is continually blocked by the system integration issues and the configuration overheads of peripheral devices. This paper presents a nonvolatile system-on-chip (NVSoC) with improved integration level, power management flexibility, and system wake-up speed. An on-chip power management subsystem is designed to minimize the number of external components while supporting versatile power policies. And a direct peripheral restore architecture is outlined, which enables a fast and parallel re-configuration of peripheral devices after the resumption of power supply. A test chip is fabricated in a 130-nm ferroelectric-CMOS process with 22.09-mm2 area. Measurement results show 6 $\times $ higher data throughput as compared with a conventional NVP when facing power failures. [ABSTRACT FROM AUTHOR]
Copyright of IEEE Journal of Solid-State Circuits is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
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An: 134907894
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  Data: A 130-nm Ferroelectric Nonvolatile System-on-Chip With Direct Peripheral Restore Architecture for Transient Computing System.
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  Data: <searchLink fieldCode="AR" term="%22Liu%2C+Yongpan%22">Liu, Yongpan</searchLink><br /><searchLink fieldCode="AR" term="%22Su%2C+Fang%22">Su, Fang</searchLink><br /><searchLink fieldCode="AR" term="%22Yang%2C+Yixiong%22">Yang, Yixiong</searchLink><br /><searchLink fieldCode="AR" term="%22Wang%2C+Zhibo%22">Wang, Zhibo</searchLink><br /><searchLink fieldCode="AR" term="%22Wang%2C+Yiqun%22">Wang, Yiqun</searchLink><br /><searchLink fieldCode="AR" term="%22Li%2C+Zewei%22">Li, Zewei</searchLink><br /><searchLink fieldCode="AR" term="%22Li%2C+Xueqing%22">Li, Xueqing</searchLink><br /><searchLink fieldCode="AR" term="%22Yoshimura%2C+Ryuji%22">Yoshimura, Ryuji</searchLink><br /><searchLink fieldCode="AR" term="%22Naiki%2C+Takashi%22">Naiki, Takashi</searchLink><br /><searchLink fieldCode="AR" term="%22Tsuwa%2C+Takashi%22">Tsuwa, Takashi</searchLink><br /><searchLink fieldCode="AR" term="%22Saito%2C+Takahiko%22">Saito, Takahiko</searchLink><br /><searchLink fieldCode="AR" term="%22Wang%2C+Zhongjun%22">Wang, Zhongjun</searchLink><br /><searchLink fieldCode="AR" term="%22Taniuchi%2C+Koji%22">Taniuchi, Koji</searchLink><br /><searchLink fieldCode="AR" term="%22Yang%2C+Huazhong%22">Yang, Huazhong</searchLink>
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  Data: <searchLink fieldCode="JN" term="%22IEEE+Journal+of+Solid-State+Circuits%22">IEEE Journal of Solid-State Circuits</searchLink>. Mar2019, Vol. 54 Issue 3, p885-895. 11p.
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  Data: Owing to its unique capability to sustain computation progress over power outages, a nonvolatile processor (NVP) is promising for energy-harvesting-powered Internet-of-Things devices. However, the widespread application of NVP is continually blocked by the system integration issues and the configuration overheads of peripheral devices. This paper presents a nonvolatile system-on-chip (NVSoC) with improved integration level, power management flexibility, and system wake-up speed. An on-chip power management subsystem is designed to minimize the number of external components while supporting versatile power policies. And a direct peripheral restore architecture is outlined, which enables a fast and parallel re-configuration of peripheral devices after the resumption of power supply. A test chip is fabricated in a 130-nm ferroelectric-CMOS process with 22.09-mm2 area. Measurement results show 6 $\times $ higher data throughput as compared with a conventional NVP when facing power failures. [ABSTRACT FROM AUTHOR]
– Name: AbstractSuppliedCopyright
  Label:
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  Data: <i>Copyright of IEEE Journal of Solid-State Circuits is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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              Text: Mar2019
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